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9037800 Speculative copying of data from main buffer cache to solid-state secondary cache of a storage server  
A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache,...
9003163 Combining a remote TLB lookup and a subsequent cache miss into a single coherence operation  
The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For...
8996839 Data storage device aligning partition to boundary of sector when partition offset correlates with offset of write commands  
A data storage device is disclosed comprising a non-volatile memory comprising a plurality of sectors. A partition map is evaluated that identifies a partition accessed through a plurality of...
8996811 Scheduler, multi-core processor system, and scheduling method  
A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal...
8972660 Disk subsystem and data restoration method  
A disk subsystem and a data restoration method with which the rise time when the disk subsystem is restored can be shortened. A disk subsystem and data restoration method whereby, when the power...
8966180 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8949537 Storage control apparatus and method for detecting write completion of data  
A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and...
8949540 Lateral castout (LCO) of victim cache line in data-invalid state  
A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect...
8943271 Distributed cache arrangement  
Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines...
8914391 Method, program, and system for converting part of graph data to data structure as an image of homomorphism  
To provide a method, program, and system for converting graph data to a data structure that enables manipulations in various applications to be reflected in the original graph data. The method...
8909872 Computer system with coherent interconnection  
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is...
8898390 Scheduling workloads based on cache asymmetry  
In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of...
8868828 Implementing storage adapter performance optimization with cache data/directory mirroring  
A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design...
8861011 Print image processing system and non-transitory computer readable medium  
A print image processing system includes plural logical page interpretation units, a dual interpretation unit, a cache memory, an assignment unit, and a print image data generation unit. The...
8862826 Method and apparatus for increasing capacity of cache directory in multi-processor systems  
A method and an apparatus for increasing capacity of cache directory in multi-processor systems, the apparatus comprising a plurality of processor nodes and a plurality of cache memory nodes and a...
8856457 Information processing system and a system controller  
In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache...
8832333 Memory system and data transfer method  
According to the embodiment, a memory system includes a first memory which includes a memory cell array and a read buffer, a second memory, a command queue, a command sorting unit, and a data...
8806134 Mirrored cache protection  
Methods of protecting cache data are provided. For example, various methods are described that assist in handling dirty write data cached in memory by duplication into other locations to protect...
RE45078 Highly efficient design of storage array utilizing multiple pointers to indicate valid and invalid lines for use in first and second cache spaces and memory subsystems  
A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is...
8799583 Atomic execution over accesses to multiple memory locations in a multiprocessor system  
A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the...
8751676 Message communication techniques  
A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network...
8738859 Hybrid caching techniques and garbage collection using hybrid caching techniques  
Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic...
8738886 Memory mapping in a processor having multiple programmable units  
A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain....
8706966 System and method for adaptively configuring an L2 cache memory mesh  
A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled...
8706968 Apparatus, system, and method for redundant write caching  
An apparatus, system, and method are disclosed for redundant write caching. The apparatus, system, and method are provided with a plurality of modules including a write request module, a first...
8700862 Compression status bit cache and backing store  
A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing...
8695011 Mixed operating performance modes including a shared cache mode  
Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined...
8677371 Mixed operating performance modes including a shared cache mode  
Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined...
8671245 Using identification in cache memory for parallel requests  
In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part...
8656128 Aggregate data processing system having multiple overlapping synthetic computers  
A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third...
8656129 Aggregate symmetric multiprocessor system  
An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second...
8626866 System and method for caching network file systems  
A network caching system has a multi-protocol caching filer coupled to an origin server to provide storage virtualization of data served by the filer in response to data access requests issued by...
8595437 Compression status bit cache with deterministic isochronous latency  
One embodiment of the present invention sets forth a compression status bit cache with deterministic latency for isochronous memory clients of compressed memory. The compression status bit cache...
8560795 Memory arrangement for multi-processor systems including a memory queue  
A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a...
8539155 Managing home cache assignment  
Managing cache memories in a computing system comprising multiple cores includes: assigning home cache locations for portions of data stored among caches in a group of caches of respective cores;...
8533402 Caching and decaching distributed arrays across caches in a parallel processing environment  
The present invention provides for automatically caching via extensions indices in a technical computing environment one or more portions of a distributed array assigned to other technical...
8521963 Managing cache coherence  
Managing data in a computing system comprising multiple cores includes: assigning a first set of data to caches within cores of a first subset of fewer than all of the cores in the computing...
8516149 System for operating NFSv2 and NFSv3 clients with federated namespace  
An information retrieval system having: a client adapted for accessing a plurality of file sets stored on one of a plurality of file servers; a plurality of file servers configured to operate with...
8489820 Speculative copying of data from main buffer cache to solid-state secondary cache of a storage server  
A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache,...
8447874 Web page data streaming  
A system generates a web page that includes a plurality of embedded data windows. The system receives a request for the web page from a browser and in response generates and displays a frame for...
8443145 Distributed memory usage for a system having multiple integrated circuits each including processors  
A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such...
8443148 System-wide quiescence and per-thread transaction fence in a distributed caching agent  
Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state...
8433772 Automated tape drive sharing in a heterogeneous server and application environment  
An approach for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer is presented. The first computer receives a message...
8369971 Media system having preemptive digital audio and/or video extraction function  
A media system is disclosed that uses preemptive recording of media files to reduce playback latency when media tracks are subsequently selected for playback during the recording process. The...
8370595 Aggregate data processing system having multiple overlapping synthetic computers  
A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third...
8370579 Global instructions for spiral cache management  
A pipelined cache memory supports global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile...
8364922 Aggregate symmetric multiprocessor system  
An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second...
8352681 Storage system and a control method for accelerating the speed of copy processing  
Proposed are a highly reliable storage system and its control method capable of accelerating the processing speed of the copy processing seen from the host device. With the storage system and its...
8341353 System and method to access a portion of a level two memory and a level one memory  
A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two...
8341355 Reducing energy consumption of set associative caches by reducing checked ways of the set association  
Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are...

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