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7613886 Methods and apparatus for synchronizing data access to a local memory in a multi-processor system  
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
7606971 Storage control apparatus and external storage apparatus  
A storage control apparatus includes a plurality of temporary storage units that are managed in a redundant manner by data mirroring, and temporarily store data input from an outside source; a...
7603488 Systems and methods for efficient memory management  
Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system...
7571242 Method for accelerated packet processing  
IPv6 has been developed as an evolutionary advance of IPv4. Although IPv6 offers considerable improvement in certain areas such as addressing and routing it has eliminated the Internet header...
7565678 Methods and devices for discouraging unauthorized modifications to set top boxes and to gateways  
Methods and devices are disclosed for discouraging unauthorized modifications to set top boxes and gateways. Resource information is received that describing the number of disk drives and/or the...
7562190 Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture  
A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability...
7552282 Method, computer readable medium, and data storage system for selective data replication of cached data  
Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache...
7536510 Hierarchical MRU policy for data cache  
A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each...
7529889 Data processing apparatus and method for performing a cache lookup in an energy efficient manner  
A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing...
7490200 L2 cache controller with slice directory and unified cache structure  
A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a...
7461210 Managing set associative cache memory according to entry type  
Managing memory includes: mediating access to a first memory as a cache for a second memory; and associating one of a plurality of entry types with entries in the cache. Data from the second memory...
7437511 Secondary level cache for storage area networks  
For use in a storage area network (SAN), a virtualization layer including at least one virtual engine having a respective local cache and a secondary cache layer, wherein the secondary cache layer...
7434001 Method of accessing cache memory for parallel processing processors  
A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members...
7421538 Storage control apparatus and control method thereof  
A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and...
7418555 Multiprocessor system and method to maintain cache coherence  
A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors....
7404044 System and method for data transfer between multiple processors  
A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In...
7395332 Method and apparatus for high-speed parsing of network messages  
A method for searching network messages for pre-defined regular expressions is disclosed. A plurality of pre-defined regular expressions are stored in a content-addressable memory (CAM). A network...
7373458 Cache memory system with multiple ports cache memories capable of receiving tagged and untagged requests  
There is described a cache memory system including a first cache memory and a second cache memory. A first port is arranged to receive a request for a first item and determine whether the first...
7370150 System and method for managing a cache memory  
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
7346744 Methods and apparatus for maintaining remote cluster state information  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for improving the...
7346738 Cache memory for a scalable information distribution system  
An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data...
7302526 Handling memory faults for mirrored memory  
Handling a faulting memory of a pair of mirrored memories includes initially causing a non-faulting memory of the pair of mirrored memories to service all read and write operations for the pair of...
7299340 Data processing device having selective data cache architecture and computer system including the same  
The disclosure is a data processing device with selective data cache architecture and a computer system including the data processing device. The data processing device is comprised of a...
7293196 Method, apparatus, and system for preserving cache data of redundant storage controllers  
A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a...
7287122 Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing  
A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache,...
7254617 Distributed cache between servers of a network  
A distributed cache module that allows for a distributed cache between multiple servers of a network without using a central cache manager. The distributed cache module transmits each message with...
7251723 Fault resilient booting for multiprocessor system using appliance server management  
A multiprocessor computer system implements fault resilient booting by using appliance server management. While previous systems have utilized fault resilient booting, it has required the use of a...
7249221 Storage system having network channels connecting shared cache memories to disk drives  
A storage system is arranged to speed up the operation and easily duplicate data without the capacity of the cache memory being so large even if lots of host computers are connected with the...
7240159 Data processor having cache memory  
A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction...
7213107 Dedicated cache memory  
A method and apparatus for a dedicated cache memory are described. Under an embodiment of the invention, a cache memory includes a general-purpose sector and a dedicated sector. The general-purpose...
7151544 Method for improving texture cache access by removing redundant requests  
Cache access is optimized through identifying redundant accesses (read-requests made to identical system memory addresses), and issuing a single cache data request for each group of redundant...
7142541 Determining routing information for an information packet in accordance with a destination address and a device address  
According to some embodiments, routing information for an information packet is determined in accordance with a destination address and a device address.
7120755 Transfer of cache lines on-chip between processing cores in a multi-core system  
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific...
7107409 Methods and apparatus for speculative probing at a request cluster  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller...
7103725 Methods and apparatus for speculative probing with early completion and delayed request  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller...
7103722 Cache configuration for compressed memory systems  
A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines...
7089372 Local region table for storage of information regarding memory access by other nodes  
Information regarding memory access by other nodes within a coherency controller of a node is locally stored. The coherency controller receives a transaction relating a line of local memory of the...
7085886 Autonomic power loss recovery for a multi-cluster storage sub-system  
An improved storage controller and method for storing and recovering data are disclosed. The storage controller includes a first cluster for directing data from a host computer to a storage device...
7076610 FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same  
An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having...
7076609 Cache sharing for a chip multiprocessor or multiprocessing system  
Cache sharing for a chip multiprocessor. In one embodiment, a disclosed apparatus includes multiple processor cores, each having an associated cache. A control mechanism is provided to allow...
7020750 Hybrid system and method for updating remote cache memory with user defined cache update policies  
A hybrid system for updating cache including a first computer system coupled to a database accessible by a second computer system, said second computer system including a cache, a cache update...
7003630 Mechanism for proxy management of multiprocessor storage hierarchies  
A method and apparatus within a processing environment is provided for proxy management of a plurality of proxy caches connected to a plurality of processing elements or cores within a unified...
6996674 Method and apparatus for a global cache directory in a storage cluster  
A method, apparatus, and article of manufacture provide the ability to maintain cache in a clustered environment. The cache is maintained in both a primary and secondary node. When data is...
6996678 Method and apparatus for randomized cache entry replacement  
A cache controller is disclosed. The cache controller includes potential replacement list, a plurality of valid bits and a number of counters. The potential replacement list includes a number of...
6996657 Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system  
An apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer that may be configured to accumulate data received on a...
6986002 Adaptive shared data interventions in coupled broadcast engines  
The present invention provides for a bus system having a local bus ring coupled to a remote bus ring. A processing unit is coupled to the local bus node and is employable to request data. A cache...
6981101 Method and system for maintaining data at input/output (I/O) interfaces for a multiprocessor system  
A multiprocessor system and method includes a processing sub-system having a plurality of processors and a processor memory system. A scalable network is operable to couple the processing...
6976125 Method and apparatus for predicting hot spots in cache memories  
One embodiment of the present invention provides a system for predicting hot spots in a cache memory. Upon receiving a memory operation at the cache, the system determines a target location within...
6970975 Method for efficient caching and enumerating objects in distributed storage systems  
A method for performing efficient caching through an enumeration process is provided. The objects residing on the storage medium are cached in the order that these objects are kept in the directory...
6959361 Distributed caching mechanism for pending memory operations within a memory controller  
One embodiment of the present invention provides a memory controller that contains a distributed cache that stores cache lines for pending memory operations. This memory controller includes an...
Matches 1 - 50 out of 242 1 2 3 4 5 >