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7624234 Directory caches, and methods for operation thereof  
A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into...
7620776 Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks  
A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to...
7613886 Methods and apparatus for synchronizing data access to a local memory in a multi-processor system  
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
7613884 Multiprocessor system and method ensuring coherency between a main memory and a cache memory  
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
7606249 Methods and systems for caching packets to be written to or read from packet memory  
Methods and systems for caching packets to improve utilization of packet memory are disclosed. In one method, packets to be written to a packet memory are accumulated in write caches on an egress...
7600080 Avoiding deadlocks in a multiprocessor system  
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a...
7589738 Cache memory management system and method  
A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The...
7584329 Data processing system and method for efficient communication utilizing an Ig coherency state  
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache...
7581064 Utilizing cache information to manage memory access and cache utilization  
In a method of utilizing cache metadata to optimize memory access, cache metadata associated with a set of cache locations is inspected by software. The cache metadata is analyzed to determine...
7577795 Disowning cache entries on aging out of the entry  
Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the...
7577690 Managing checkpoint queues in a multiple node system  
Techniques are provided for managing caches in a system with multiple caches that may contain different copies of the same data item. Specifically, techniques are provided for coordinating the...
7577059 Decoding control with address transition detection in page erase function  
Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A...
7574572 Cache memory, system, and method of storing data  
A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data...
7574562 Latency-aware thread scheduling in non-uniform cache architecture systems  
A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data....
7565399 Caching web objects transformed by a pipeline of adaptation services  
In one embodiment, a method for processing a client request for content comprises receiving, at an intermediary network node, a client request for content on a network. The client request is...
7562190 Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture  
A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability...
7552282 Method, computer readable medium, and data storage system for selective data replication of cached data  
Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache...
7549021 Enhanced data integrity using parallel volatile and non-volatile transfer buffers  
Method and apparatus for transferring data. The apparatus preferably includes a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a...
7546353 Managed peer-to-peer applications, systems and methods for distributed data access and storage  
Applications, systems and methods for efficiently accessing data and controlling storage devices among multiple computers connected by a network. Upon receiving a request for access to data...
7543123 Multistage virtual memory paging system  
A computer implemented hierarchical method for paging data, when evicting a page of data from the computer system main storage, evicting the page to a first paging store (preferably NVRAM). When...
7543042 Remote access method for accessing dynacache data  
A method for accessing an internal dynamic cache of a Websphere-type Application Server (WAS) from an external component that includes the step of establishing a software interface component within...
7539819 Cache operations with hierarchy control  
An improved approach to cache management is disclosed which may be implemented to provide fine-grained control over individual caches or subsets of a multi-level cache hierarchy. By selectively...
7536692 Thread-based engine cache partitioning  
In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled...
7536510 Hierarchical MRU policy for data cache  
A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each...
7536421 Intelligent client architecture computer system and method  
A collision detection and data synchronization mechanism operates to expand the speed and capability of distributed applications. The execution environment employs collision detection and data...
7529889 Data processing apparatus and method for performing a cache lookup in an energy efficient manner  
A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing...
7529799 Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
7529139 N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof  
Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a...
7523265 Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache  
Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the...
7519774 Data processor having a memory control unit with cache memory  
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
7512738 Allocating call stack frame entries at different memory levels to functions in a program  
Provided are a method, system, and program for allocating call stack frame entries at different memory levels to functions in a program. Functions in a program accessing state information stored in...
7509457 Non-homogeneous multi-processor system with shared memory  
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
7502775 Providing cost model data for tuning of query cache memory in databases  
Providing cost model data for tuning query cache memory size in database systems. In one aspect, a query is received, and a query cache is checked for a stored query matching the received query. In...
7500065 Data processing system and method for efficient L3 cache directory management  
A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state...
7496726 Controlling contention via transactional timers among conflicting transactions issued by processors operating in insistent or polite mode  
A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if...
7496712 Proximity communication-based off-chip cache memory architectures  
A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a...
7484062 Cache injection semi-synchronous memory copy operation  
A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a...
7480772 Data processing system and method for efficient communication utilizing an Tn and Ten coherency states  
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory...
7480759 System, method and storage medium for providing data caching and data compression in a memory subsystem  
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory...
7480731 Data transfer scheme using caching technique for reducing network load  
In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices,...
7478203 Technique for eliminating dead stores in a processor  
A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the...
7478202 Using the message fabric to maintain cache coherency of local caches of global memory  
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
7475196 Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains  
A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor...
7472224 Reconfigurable processing node including first and second processor cores  
In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The...
7472219 Data-storage apparatus, data-storage method and recording/reproducing system  
A data-storage apparatus, a data-storage method and a recording/reproducing system are provided, which effectively use the time elapsing before data is transferred to be written in a recording...
7469322 Data processing system and method for handling castout collisions  
A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and...
7469318 System bus structure for large L2 cache array topology with different latency domains  
A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock...
7464223 Storage system including storage adapters, a monitoring computer and external storage  
A storage system having a cluster configuration that prevents a load from concentrating on a certain storage node and enhances access performance is disclosed. The storage system is provided with...
7461207 Methods and apparatus for controlling hierarchical cache memory  
Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory...
7454585 Efficient and flexible memory copy operation  
A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a...
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