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7606969 |
Programmable logic devices
An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register...
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7583663 |
Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath
A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during...
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7568066 |
Reset system for buffer and method thereof
A reset system for a buffer and a method thereof are disclosed. The reset system of the present invention includes a resettable flag in the buffer and a control unit. The reset method is to set the...
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7548472 |
Logic embedded memory having registers commonly used by macros
A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has...
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7523353 |
Method for detecting hang or dead lock conditions
A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user...
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7512311 |
Data output apparatus and method with managed buffer
A data output apparatus includes a disk drive for driving a magneto-optical disk. Compressed image data recorded on the magneto-optical disk is transferred from the magneto-optical disk to an SDRAM...
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7509451 |
Method and circuit for updating a software register in semiconductor memory device
A method and circuit for updating a software register is disclosed, wherein the software register is updated using data received through a data I/O pad, and the updated data is read and transferred...
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7484061 |
Method for performing swap operation and apparatus for implementing the same
A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a...
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7467274 |
Method to increase the life span of limited cycle read/write media
A file system technique extends the life cycle of limited read/write media. Rewrite cycles of each file and/or each region of the media may be tracked. Different regions of the media are classified...
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7451261 |
Data storage device and control method with buffer control thereof
Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used...
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7440532 |
Bit slip circuitry for serial data signals
Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register...
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7421559 |
Apparatus and method for a synchronous multi-port memory
A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access...
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7409717 |
Metamorphic computer virus detection
The executions of computer viruses are analyzed to develop register signatures for the viruses. The register signatures specify the sets of outputs the viruses produce when executed with a given...
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7392417 |
Device for exchanging data signals between two clock domains
A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory...
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7346739 |
First-in-first-out memory system and method for providing same
First-in-first-out (FIFO) memory system and method for providing the same is described. In one example, a dual-port memory circuit includes first storage locations for defining a plurality of...
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7334063 |
Method and device for register access according to identifier register
A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a...
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7287169 |
Electronic device and timer therefor with tamper event stamp features and related methods
An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may...
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7254670 |
System, method, and apparatus for realizing quicker access of an element in a data structure
This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base...
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7200724 |
Two dimensional data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
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7165143 |
System and method for manipulating cache data
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
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7162608 |
Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs,...
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7162573 |
Communication registers for processing elements
Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For...
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7152153 |
Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction
A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single...
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7148826 |
Data input circuit and semiconductor device utilizing data input circuit
A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit...
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7130857 |
Method for accessing a memory unit in which sequences of notes are stored, corresponding memory unit and corresponding program
A method employs a bit sequence having a plurality of successive bits is stored in a write mode in a memory unit for a data value of a datum. The bit positions are each allocated to a data set...
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7126601 |
Graphics memory system that utilizes detached-Z buffering in conjunction with a batching architecture to reduce paging overhead
A graphics memory system of a graphics display system which utilizes a batching architecture in conjunction with detached Z buffering to minimize paging overhead is disclosed. The graphics memory...
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7120744 |
System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
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7117316 |
Memory hub and access method having internal row caching
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory...
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7107393 |
Systems and method for transferring data asynchronously between clock domains
An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock...
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7103719 |
System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
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7095742 |
Packet processing unit
A packet receiving circuit splits the packet received from a transmission channel into a fixed length of cells and outputs the cells, a search key extracting circuit extracts a predetermined search...
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7093084 |
Memory implementations of shift registers
A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of...
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7092301 |
Controller and method for writing data
The present invention provides a controller that can write an operation program for a control circuit to a memory and a method for writing data, while suppressing an increase in circuit area and an...
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7080216 |
Data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
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7073019 |
Method and apparatus for assembling non-aligned packet fragments over multiple cycles
A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data...
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7051153 |
Memory array operating as a shift register
A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an...
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7028149 |
System and method for resetting a platform configuration register
A method and apparatus for resetting and modifying special registers in a security token is described. In one embodiment, a register may be reset when a reset flag is true when a special...
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6996665 |
Hazard queue for transaction pipeline
A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another...
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6986089 |
Power reduction in scannable D-flip-flop with synchronous preset or clear
In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal....
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6985993 |
Control register assembly
A control register assembly controls components to be controlled in an electric circuit. The control register assembly includes a control register. The control register is formed by at least one...
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6978344 |
Shift register control of a circular elasticity buffer
A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the...
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6957309 |
Method and apparatus for re-accessing a FIFO location
In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the...
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6952756 |
Method and apparatus for speculative loading of a memory
The present invention provides a speculatively loaded memory for use in a data processing system. The present invention may include a memory block including rows each identified by an address. A...
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6948030 |
FIFO memory system and method
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic....
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6941418 |
Integrated circuit and method outputting data
A circuit according to an embodiment of the present invention can load data in parallel to a barrel shifter, and output data to a pipelined multiplexer stage. The multiplexer is used to direct data...
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6920595 |
Skewed latch flip-flop with embedded scan function
A flip-flop circuit with embedded scan capabilities uses a skewed latch to pull one end of the flip-flop either up or down while another end of the flip-flop is active. Further, the flip-flop is...
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6920526 |
Dual-bank FIFO for synchronization of read data in DDR SDRAM
The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One...
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6901490 |
Read/modify/write registers
The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be...
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6886048 |
Techniques for processing out-of-order requests in a processor-based system
A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with...
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6882656 |
Speculative transmit for system area network latency reduction
A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit...
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