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7620783 Method and apparatus for obtaining memory status information cross-reference to related applications  
In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory...
7617356 Refresh port for a dynamic memory  
A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh...
7617355 Parity-scanning and refresh in dynamic memory devices  
A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the...
7613941 Mechanism for self refresh during advanced configuration and power interface (ACPI) standard C0 power state  
An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle...
7613873 Deferring refreshes during calibrations in memory systems  
A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams....
7610433 Memory controller interface  
A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND...
7603493 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction  
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
7603512 Dynamic memory refresh controller, memory system including the same and method of controlling refresh of dynamic memory  
A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a...
7600065 Arbitration scheme for shared memory device  
For arbitrating access to a shared memory device among a plurality of masters, a master generates a request for access signal that is sent to the arbitrator concurrently with an indispensable...
7591022 Content addressable information encapsulation, representation, and transfer  
Representing a number of assets on an originating computer begins with selecting the assets to be represented. Cryptographic hash asset identifiers are generated; each of the asset identifiers is...
7587545 Shared memory device  
A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory...
7565480 Dynamic memory supporting simultaneous refresh and data-access transactions  
Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The...
7565479 Memory with refresh cycle donation to accommodate low-retention-storage rows  
In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per...
7558144 Circuit for controlling pulse width of auto-refresh signal and circuit for generating internal row address for auto refresh  
A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and...
7558908 Structure of sequencers that perform initial and periodic calibrations in a memory system  
A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these...
7551505 Memory refresh method and apparatus  
An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows...
7543130 Digital signal processor for initializing a ram  
A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that...
7543106 Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips  
A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to...
7526602 Memory control system and memory control circuit  
A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for...
7519762 Method and apparatus for selective DRAM precharge  
Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is...
7516270 Memory controller and method for scrubbing memory without using explicit atomic operations  
A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by...
7509511 Reducing register file leakage current within a processor  
A method for reducing leakage current within a register file of a processor is disclosed. The register file within the processor is partitioned into at least two power domains, and each of the two...
7506126 Detection circuit for mixed asynchronous and synchronous memory operation  
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals,...
7500115 Information handling system including a memory device capable of being powered by a battery  
An information handling system (IHS) includes a processor, a memory module coupled to the processor, a memory device, and a power source, coupled to the memory device, for supplying power to the...
7496777 Power throttling in a memory system  
A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is...
7460127 Display control circuit  
A display control circuit incorporating a RAM in which display data is stored, comprises an oscillation circuit which oscillates a reference clock to define a transfer period in which the display...
7453752 Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder  
A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-array j while filling the row R i (where i≠j) corresponding...
7454586 Memory device commands  
Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In...
7444577 Memory device testing to support address-differentiated refresh rates  
A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from...
7437500 Configurable high-speed memory interface subsystem  
A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a...
7436728 Fast random access DRAM management method including a method of comparing the address and suspending and storing requests  
A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying...
7433996 System and method for refreshing random access memory cells  
A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an...
7392339 Partial bank DRAM precharge  
A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second...
7379323 Memory with a refresh portion for rewriting data  
This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies...
7379370 Semiconductor memory  
After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in...
7370140 Enhanced DRAM with embedded registers  
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are...
7366828 Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device  
A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that...
7356642 Deferring refreshes during calibrations in memory systems  
A method, an apparatus, and a computer program are provided to control refreshes in Extreme Data Rate (XDR™) memory systems. XDR™ memory systems employ calibrations to ensure the precise...
7353329 Memory buffer device integrating refresh logic  
Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus...
7350018 Method and system for using dynamic random access memory as cache memory  
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In...
7343502 Method and apparatus for dynamic DLL powerdown and memory self-refresh  
Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in...
7343457 Dual active bank memory controller  
A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a...
7342841 Method, apparatus, and system for active refresh management  
A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the...
7330921 Communication control circuit and communication control method  
A communication control circuit that performs the process of receiving a response to send data in synchronous transfer mode within a certain period of time without using an external control...
7330928 Semiconductor device and electronic instrument  
A semiconductor device including: a DRAM which is a volatile memory; a PLL circuit which outputs an operation clock signal generated by multiplying an input clock signal; a circuit block which...
7330926 Interruption control system  
An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status...
7328304 Interface for a block addressable mass storage system  
A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories.
7325090 Refreshing data stored in a flash memory  
Data are stored in one or more cells of a non-volatile memory, and are refreshed according to a predetermined condition. The data are refreshed either in-place or out-of-place. The condition may be...
7325100 Apparatus and method for entering and exiting low power mode  
An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management...
7315970 Semiconductor device to improve data retention characteristics of DRAM  
A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and...
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