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9037811 Tagging in memory control unit (MCU)  
Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command...
9032134 Methods of operating a memory system that include outputting a data pattern from a sector allocation table to a host if a logical sector is indicated as being erased  
A method of operating a memory system includes receiving a read command from a host, where the read command is associated with a logical sector of a memory, determining whether the logical sector...
9032136 Memory controller for memory with mixed cell array and method of controlling the memory  
A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space...
9032166 Memory arbitration system and method having an arbitration packet protocol  
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including...
9032398 Online classification of memory pages based on activity level represented by one or more bits  
Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The...
9026714 Memory expansion using rank aggregation  
In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping...
9025409 Memory buffers and modules supporting dynamic point-to-point connections  
A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device...
9026725 Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals  
Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first...
9026726 Data read/write system  
The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data...
9026746 Signal control device and signal control method  
A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports,...
9021176 Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same  
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache...
9021193 Utilization of stored timing data to configure a memory controller  
A method for configuring a memory controller including determining whether a serial number of at least one memory module matches a stored serial number corresponding to at least one of the memory...
RE45486 Method for addressing a memory card, a system using a memory card, and a memory card  
The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to...
9015440 Autonomous memory subsystem architecture  
An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on...
9015408 Load reduction dual in-line memory module (LRDIMM) and method for programming the same  
A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory...
9015389 Volatile memory device and memory controller  
A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a...
9009400 Semiconductor memory systems with on-die data buffering  
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an...
9009392 Leveraging a hybrid infrastructure for dynamic memory allocation and persistent file storage  
Dynamic allocation of memory in a hybrid system is provided. In particular, a method and system is provided to leverage a hybrid infrastructure for dynamic memory allocation and persistent file...
9003110 Dividing incoming data into multiple data streams and transforming the data for storage in a logical data object  
Various embodiments for storing a logical object are provided. In one such embodiment, by way of example only, incoming data is divided corresponding to a logical data object into a plurality of...
8996822 Multi-device memory serial architecture  
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second...
8995137 Modular mass storage system and method therefor  
A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed...
8990489 Multi-rank memory module that emulates a memory module having a different number of ranks  
A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a...
8990490 Memory controller with reconfigurable hardware  
Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory...
8990492 Increasing capacity in router forwarding tables  
Aspects of the disclosure provide for increasing the capacity of ternary content addressable memories (TCAMs). For example, one aspect provides a method for adding rules to a TCAM, wherein the...
8990491 Eye scan for asymmetric shaped communication signal  
Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a...
8984216 Apparatus, system, and method for managing lifetime of a storage device  
Apparatuses, systems, and methods are disclosed for managing lifetime for a data storage device. A target module determines a write bandwidth target for a data storage device. An audit module...
8984215 Dividing incoming data into multiple data streams and transforming the data for storage in a logical data object  
Various embodiments for storing a logical object are provided. In one such embodiment, by way of example only, incoming data is divided corresponding to a logical data object into a plurality of...
8977822 Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same  
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The...
8977811 Scalable schedulers for memory controllers  
Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a...
8977809 Sharing resources in multi-dice stacks  
Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided....
8977810 Systems and methods for using memory commands  
Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller...
8977806 Hybrid memory module  
One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module...
8972685 Method, apparatus and system for exchanging communications via a command/address bus  
Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command...
8972620 Methods and systems to simplify population of modular components in an information handling system  
Systems and methods to simplify population of modular components in an information handling system are disclosed. A method of populating modular components in an information handling system...
8966166 Information processing apparatus and information processing method  
There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an...
8966208 Semiconductor memory device with plural memory die and controller die  
A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a...
8966179 Volatile memory storage for private web browsing  
Computer-implemented methods for temporarily storing history of a web browsing session are provided. In one aspect, the method includes receiving a request to temporarily store session information...
8959271 System and method for accessing memory  
A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory...
8959298 System and method for managing performance of a computing device having dissimilar memory types  
Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory...
8954687 Memory hub and access method having a sequencer and internal row caching  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory...
8948212 Memory controller with circuitry to set memory device-specific reference voltages  
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical...
8949519 Simulating a memory circuit  
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such...
8943267 Management of memory refresh power consumption  
Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The...
8938578 Memory device with multi-mode deserializer  
An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface...
8935472 Processing device with independently activatable working memory bank and methods  
A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently...
8930616 System refresh in cache memory  
System refresh in a cache memory that includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory and activating a refresh request at the...
8924679 Memory device and memory system including the same  
A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a...
8924639 Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules  
Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502)...
8918618 Adaptive memory system for enhancing the performance of an external computing device  
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static...
8918580 Storage device with buffer memory including non-volatile RAM and volatile RAM  
A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer...