|
Match
|
Document |
Document Title |
|
|
7257652 |
Method and system for filesystem mounted on a root directory wherein data is redirected from a first storage system to a second storage system
An automated method of establishing a filesystem utilizing the establishment of a first filesystem that interfaces with devices by loading software, including a first set of drivers, into memory...
|
|
|
7256790 |
Video and graphics system with MPEG specific data transfer commands
A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video...
|
|
|
7254668 |
Method and apparatus for grouping pages within a block
Methods and apparatus for efficiently enabling pages within a block to be accessed are disclosed. According to one aspect of the present invention, a method for writing data into a first block in a...
|
|
|
7254813 |
Method and apparatus for resource allocation in a raid system
The present invention implements an I/O task architecture in which an I/O task requested by the storage manager, for example a stripe write, is decomposed into a number of lower-level asynchronous...
|
|
|
7254667 |
Data transfer between an external data source and a memory associated with a data processor
A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with...
|
|
|
7254690 |
Pipelined semiconductor memories and systems
The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor...
|
|
|
7254680 |
Semiconductor integrated circuit and data processing system
To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense...
|
|
|
7254666 |
System and method for delivering information at inaccessible locations
Systems and methods of using the systems for delivering information related to an inaccessible location to individuals at the inaccessible location are disclosed. The system comprises a memory...
|
|
|
7254675 |
Memory system having memory modules with different memory device loads
A memory system system includes a single in-line memory module (SIMM) which contains a memory device and a signal transmission line connected between the memory device and a connection terminal,...
|
|
|
7251710 |
Cache memory subsystem including a fixed latency R/W pipeline
A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The...
|
|
|
7249235 |
Architecture for a scalable and user-extensible heap dump analysis tool
A heap analyzer that processes a snapshot of the heap contained in a dump file is described. The heap analyzer tool can be configured to relocate the pointers in the dumped heap and allow...
|
|
|
7249228 |
Reducing the number of block masks required for programming multiple access control list in an associative memory
Mechanisms for reducing the number of block masks required for programming multiple access control lists in an associative memory are disclosed. A combined ordering of masks corresponding to...
|
|
|
7249220 |
Storage system
To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data...
|
|
|
7249206 |
Dynamic memory allocation between inbound and outbound buffers in a protocol handler
An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the...
|
|
|
7248594 |
Efficient multi-threaded multi-processor scheduling implementation
A system and method of scheduling packets in a multi-threaded, multiprocessor network architecture provides enhanced speed and performance. The architecture involves a scheduler thread that...
|
|
|
7249270 |
Method and apparatus for placing at least one processor into a power saving mode when another processor has access to a shared resource and exiting the power saving mode upon notification that the shared resource is no longer required by the other processor
The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform...
|
|
|
7246206 |
Method and device for storing a computer program in a program memory of a control unit
A method and a device for storing a computer program in a program memory of a control unit. The computer program is stored according to predefinable rules in specific memory areas of the program...
|
|
|
7246207 |
System and method for dynamically performing storage operations in a computer network
Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection...
|
|
|
7246215 |
Systolic memory arrays
A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency...
|
|
|
7243856 |
Loading internal applications on a smartcard
Portable smartcard devices, methods of executing program code using smartcard devices, and computer readable storage media including instructions for smartcard devices are provided. According to...
|
|
|
7246281 |
Enhancements to data integrity verification mechanism
A method and apparatus is provided for maintaining data integrity. According to the method, a physical checksum calculation is performed on a block of data. After performing the physical checksum...
|
|
|
7243184 |
Maintaining packet order using hash-based linked-list queues
Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded...
|
|
|
7242635 |
Semiconductor integrated circuit device, data processing system and memory system
The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an...
|
|
|
7240155 |
Decision mechanisms for adapting RAID operation placement
A client node of a distributed storage system adaptive determines on an operation-by-operation basis whether to process a network-RAID IO operation (IO request) locally at the client node or to...
|
|
|
7237049 |
Multimedia/secure digital cards and adapters for interfacing using voltage levels to determine host types and methods of operating
A Multimedia (MMC)/Secure Digital (SD) form-factor compliant card apparatus can include a mode determining circuit connected to first and second pins of the card apparatus and configured to...
|
|
|
7237045 |
Apparatus and method for storage processing through scalable port processors
A system including a storage processing device with an input/output module. The input/output module has port processors to receive and transmit network traffic. The input/output module also has a...
|
|
|
7237133 |
Power supply control circuit for memories, method thereof and apparatus equipped with memories
The power consumption is lowered in an apparatus equipped with memories. Assuming that memories are, for example, of DRAM type, each usage circumstance of DRAM modules on a chip is observed by an...
|
|
|
7234029 |
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are...
|
|
|
7228381 |
Storage system using fast storage device for storing redundant data
A computer storage system includes a controller and a storage device array. The storage device array may include a first sub-array and a fast storage device sub-array. The first sub-array includes...
|
|
|
7228377 |
Semiconductor integrated circuit device, IC card, and mobile terminal
In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an...
|
|
|
7228472 |
System and method to control data capture
One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a...
|
|
|
7225443 |
Stack usage in computer-related operating systems
Methods, devices, configuration tools and operating systems are disclosed for reducing memory and processor usage in a computer operating system utilising a processor, a memory and a single stack,...
|
|
|
7225098 |
Monitoring device with optimized buffer
The invention concerns a monitoring device ( 18 ) integrated to a microprocessor chip ( 12 ) executing a series of instructions comprising: device ( 26 ) for producing simultaneously several types...
|
|
|
7225306 |
Efficient address generation for Forney's modular periodic interleavers
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum....
|
|
|
7225256 |
Impersonation in an access system
The present invention pertains to a system for managing network access to resources that allows a first entity to impersonate a second entity. In one embodiment, the first entity can impersonate...
|
|
|
7222221 |
Maintaining coherency of derived data in a computer system
A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer...
|
|
|
7222062 |
Method and system to support a trusted set of operational environments using emulated trusted hardware
A method and system to emulate a trusted platform module to execute trusted operations. A virtual machine monitor is executed to support a virtual machine session. An operating system is loaded...
|
|
|
7219205 |
Memory controller device
A memory controller device. The memory controller includes a first circuit to capture a first bit of data in response to a rising edge of a strobe signal and a second circuit to capture a second...
|
|
|
7219196 |
Process for managing system stacks in microcontrollers, corresponding device and computer program product
In order to manage, in the interrupt stage, a memory stack associated with a microcontroller according to a Program Counter signal and to a Condition Code Register signal that can be contained in...
|
|
|
7219185 |
Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of...
|
|
|
7215251 |
Method and apparatus for controlled persistent ID flag for RFID applications
A Radio-Frequency Identification (RFID) transponder is provided. The RFID transponder may include a basic ID flag circuit having a VDD voltage node, an output voltage node, and a capacitor coupled...
|
|
|
7213120 |
Circuit for prevention of unintentional writing to a memory, and semiconductor device equipped with said circuit
A circuit for prevention of unintentional writing to a memory prevents unintentional writing to a nonvolatile memory, after a recovery from a transitory power failure. The circuit includes a...
|
|
|
7212307 |
Image data storage system
A CPU determines whether the intended use of the image data to be stored in a plurality of HDDs has a first-type purpose, which requires storing temporarily stored image data for carrying out...
|
|
|
7210010 |
Efficient system and method for updating a memory device
A system and method for updating a binary image stored across a block-structured memory device, such as a flash memory device. From comparison of original and new images, an update package is...
|
|
|
7210001 |
Methods of and apparatus for efficient buffer cache utilization
Efficient buffer cache utilization frees a data buffer as soon as data buffer processing is completed, and without losing association of the freed data buffer and a descriptor buffer. Separate free...
|
|
|
7206892 |
Method for managing recorded streams in a rewritable recording medium
The present invention relates to a method for managing playlists of a rewritable recording medium in order to prevent unlimited playback or illegal edition of television broadcast programs or...
|
|
|
7206919 |
Rapid partial configuration of reconfigurable devices
A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit...
|
|
|
7206832 |
Method and system of managing an access to a storage system in a computer system
The Computer System consists of components including more than one Computer and Storage Subsystem to which more than one Computer are connected. The Storage Subsystem is equipped with more than one...
|
|
|
7206891 |
Multi-port memory controller having independent ECC encoders
A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has...
|
|
|
7206310 |
Method and apparatus for replicating packet data with a network element
A method and apparatus for replicating packet data within a network element are described herein. In one embodiment, a method includes storing packet data within a storage element, maintaining a...
|