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7624211 Method for bus width negotiation of data storage devices  
There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is...
7620756 Method and apparatus for updating wide storage array over a narrow bus  
A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch...
7587535 Data transfer control device including endian conversion circuit with data realignment  
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
7584314 Universal serial-to-parallel and parallel-to-serial cable interface and method  
A universal cable interface and associated system and method are provided for coupling a transmission medium to a processing device. The universal cable interface can selectively operate in a first...
7574541 FIFO sub-system with in-line correction  
A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first...
7558892 Processing device peripheral with integral network interface circuitry  
A peripheral connectable to a processing device includes a housing and network interface circuitry at least partially enclosed within the housing, the network interface circuitry being utilizable...
7555574 Asymmetric data path media access controller  
A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive...
7543088 Various methods and apparatuses for width and burst conversion  
Methods and apparatuses are described for a communication system. The communication system comprises an initiator core supporting a first burst capability as well as a target core supporting a...
7506328 Method and system for optimizing performance of an apparatus  
A method for optimizing performance of an apparatus includes interrogating at least one part of the apparatus to obtain information about the at least one part. Once the at least one part is...
7490181 Data reproducing apparatus for transforming external input signal and method thereof  
A DVD reproducing device is capable of being connected to a certain external electronic device. The DVD reproducing device includes an external input receiving unit connected with the external...
7480756 Electronic data processing circuit that transmits packed words via a bus  
An electronic data processing circuit contains a plurality of data handling units ( 10 a-d, 16 a-b) with data outputs, at least part of the data handling units having address outputs. The data...
7472250 Storage control device, and control method for storage control device  
The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks,...
7457904 Methods and systems for a reference clock  
In at least some embodiments, a method comprises receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system and activating at least one...
7447932 Semiconductor data processing device and data processing system  
Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The...
7433980 Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports  
Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input...
7421479 Network system, network control method, and signal sender/receiver  
A network system connects with processes P 1 to P 5 that can mutually send and receive a broadcast message specified with no destination and a message specified with a specific process portion...
7418530 Storage device and method for controlling storage device packet size  
The present invention variably controls the packet size that is used within a storage device in accordance with the communication environment outside the storage device. The storage device...
7376780 Protocol converter to access AHB slave devices using the MDIO protocol  
A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the...
7376777 Performing an N-bit write access to an M×N-bit-only peripheral  
A system-on-chip ( 100 ) includes a 16-bit DSP ( 102 ), a 16-bit data bus ( 202 ) coupled to the DSP, at least one 32-bit-only peripheral ( 110 ), a 32-bit data bus ( 212 ) coupled to the...
7376767 Distributed buffering system having programmable interconnecting logic and applications thereof  
A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device....
7350001 Method and apparatus for automatic word length conversion  
Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data...
7328299 Interface for compressed data transfer between host system and parallel data processing system  
An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the...
7319702 Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments  
A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the...
7308536 System bus read data transfers with data ordering control bits  
A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to...
7308514 Configuring a communication link interface  
Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of...
7286067 Appliance with communication protocol emulation  
An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The...
7281066 Memory access system including support for multiple bus widths  
A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second...
7280051 Transmission and reception of a decomposed digitized signal  
A voice signal is transmitted in an MOST network on a single channel. The width of the transmitted voice data words is preferably up to 14 bits, and each voice data word is transmitted into...
7243172 Fragment storage for data alignment and merger  
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to...
7216185 Buffering apparatus and buffering method  
Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line...
7210008 Memory controller for padding and stripping data in response to read and write commands  
A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry,...
7206876 Input/output interface of an integrated circuit device  
An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M...
7200697 High speed data transfer between mainframe storage systems  
A method and apparatus for transferring data between storage systems including a first disk system for receiving first data in a variable length data format from a host, storing the first data and...
7197625 Alignment and ordering of vector elements for single instruction multiple data processing  
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
7174398 Method and apparatus for implementing data mapping with shuffle algorithm  
A method and apparatus are provided for implementing data mapping using a shuffle algorithm. An output shuffler and an input shuffler convert a physical data group to a plurality of data subgroups....
7171496 Data bus width conversion apparatus and data processing apparatus  
A data bus width conversion apparatus is provided for receiving N-bit data from a first device having a first bus width and outputting the N-bit data to a second device having a second bus width....
7152131 Data processor having an access size control unit  
In a data processor including a master circuit that issues an access request and slave circuits that perform processing in response to the access request received from the master circuit, the...
7146566 Method and system for multiformat presentation  
Data is stored in multiple formats based on the nature of the data and the characteristics of the possible output devices to minimize processing requirements and processing time while maximizing...
7130952 Data transmit method and data transmit apparatus  
In an arrangement in which a CPU transmits data such as audio data through a 32-bit data bus, a format conversion device and a format conversion program are a are newly prepared. Further, input...
7103702 Memory device  
A memory device is so adapted that data processing time is not prolonged even when there is little bus width. A DRAM is connected to first to third buffer circuits by buses, which have a bus width...
7092439 Means and method of data encoding and communication at rates above the channel bandwidth  
The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets...
7076590 Asic expansion module for PDA  
Once attached to a slot of a personal digital assistant, a card module executes an application-specific program and transmits a result obtained thereby to the personal digital assistant. The thus...
7058745 Data terminal equipment  
Once attached to a slot of a personal digital assistant, a card module executes an application-specific program and transmits a result obtained thereby to the personal digital assistant. The thus...
7058736 Reordering of burst data transfers across a host bridge  
A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.
7051126 Hardware accelerated compression  
A compression system is arranged to use software and/or hardware accelerated compression techniques to increase compression speeds and enhance overall data throughput. A logic circuit is arranged...
7043592 External bus controller  
An external bus controller which is configured such that, when an external device having a data width smaller than that of an external bus is connected to the external bus, the signal lines of the...
7020726 Methods and apparatus for signaling to switch between different bus bandwidths  
The present invention provides an apparatus and method for selecting bus-width formats. In an exemplary preferred embodiment of the invention, the circuit includes a bus controller configured to...
7007127 Method and related apparatus for controlling transmission interface between an external device and a computer system  
A method and a related apparatus for controlling a transmission interface between a computer system and an external device is disclosed. The external device includes a bridge circuit for...
7006527 Multistage pipeline bit conversion  
A system and method that converts a series of input data words at a first data width to a series of output data words at a smaller data width. In order to achieve 10-Gigabit Ethernet over an...
6941426 System for head and tail caching  
A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail...
Matches 1 - 50 out of 179 1 2 3 4 >