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7631116 Method and system for packet encryption  
A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to...
7624310 System and method for initializing a memory system, and memory device and processor-based system using same  
Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read...
7617339 Serial interface circuit for data transfer  
A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral...
7613853 Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same  
An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and...
7606955 Single wire bus for connecting devices and methods of operating the same  
A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective...
7590789 Optimizing clock crossing and data path latency  
In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct...
7590026 Access to printing material container  
The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the...
7581045 Method, system, and article of manufacture for mapping programming interfaces  
Provided are a method, system, and article of manufacture for mapping programming interfaces. A synchronous request for reading data is received. An asynchronous request to fill selected buffers of...
7581044 Data transmission method and system using credits, a plurality of buffers and a plurality of credit buses  
A data flow management system and method in which the application and its clients are made aware of the available credits for each type of transfer before the transfer is attempted. This enables...
7571267 Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews  
Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a...
7570727 Data transmission controller and sampling frequency converter  
In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been...
7558893 Latency optimized data alignment racheting scheme  
A system, method and apparatus for aligning data sequentially received on multiple single-byte data paths are provided. A sufficient number of bytes received in each channel may be stored (e.g.,...
7552256 Network device interface for digitally interfacing data channels to a controller via a network  
A communications system and method are provided for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network...
7548994 Disk initiated asynchronous event notification in an information handling system  
A SAS target device, e.g., SAS disk, may instantiate an asynchronous event notification (AEN) transaction while still conforming to SAS protocol standards. When the SAS target has an event queued...
7546411 Digital device configuration and method  
An electromechanical data storage arrangement is interfaced with a host. The interface may include a conductor that carries read and write gate signals. Another conductor carries both a servo sync...
7543090 Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout  
An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an...
7539793 Synchronized multichannel universal serial bus  
The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
7519743 Multimedia storage and communication device and its determining method  
The present invention is related to an interface design for multimedia data transmitting, which can provide a working interface in a data storing device or a communication device, using the working...
7519742 Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission  
A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of...
7516255 Method and apparatus for providing a low-latency connection between a data processor and a remote graphical user interface over a network  
A pair of processing modules and methods that enable low latency communications between a data processing system and devices located at a remote graphic user interface across a standard shared...
7496728 Asynchronous jitter reduction technique  
The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency xf n where x is a whole integer and f n is the...
7496704 Information processing device with display having attachable/detachable data storage device having a plurality of recording media  
An information processing device includes: an interface to/from which a recording medium is attachable/detachable; a data storage device that stores data; a data extractor that extracts data...
7490179 Device for, method of, and program for dynamically switching modes for writing transaction data into disk  
A data writing device capable of dynamically switching between a write-through mode and a write-behind mode for writing transaction data into a disk including: a memory with a queue management...
7475176 High bandwidth split bus  
A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing...
7457322 System and method for multi-chassis configurable time synchronization  
Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between...
7450678 Asynchronous signal input apparatus and sampling frequency conversion apparatus  
In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A...
7450457 Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory  
A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller....
7437491 Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM  
Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on...
7430660 Data transmission apparatus, system and method, and image processing apparatus  
A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a...
7424559 Input/output upper and lower byte control device using nonvolatile ferroelectric register  
An input/output byte control device using a nonvolatile ferroelectric register can maintain compatibility with various memories by selectively controlling bytes of input/output data. Since bytes of...
7409474 Method and system for rate adaptation  
A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control...
7406548 Systems and methods for responding to a data transfer  
Systems and methods for responding to a data transfer are disclosed. One embodiment comprises a method that includes the following steps: determining a sustainable data transfer rate for data...
7386659 Memory system  
A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the...
7383372 Bus system, station for use in a bus system, and bus interface  
The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said...
7366943 Low-latency synchronous-mode sync buffer circuitry having programmable margin  
Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference...
7363440 System and method for dynamically accessing memory while under normal functional operating conditions  
A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a...
7353356 High speed, low current consumption FIFO circuit  
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
7340633 Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device  
The present invention provides a method for automatic identification of the clock frequency of a system clock ( 15 ) for the configuration of a peripheral device ( 12 ), having the following steps:...
7318075 Enhanced tabular data stream protocol  
Systems and methodologies are provided as part of a computing environment that implements an enhanced tabular data stream (TDS) protocol. Such enhanced TDS protocol can mitigate synchronization...
7305501 Portable computer system having LCD monitor for selectively receiving video signals from external video signal input from external computer  
A portable computer system includes a portable computer equipped with a graphic chip, and an LCD monitor receiving a video signal from the graphic chip and displaying the video signal. The portable...
7302505 Receiver multi-protocol interface and applications thereof  
A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a...
7302450 Workload scheduler with resource optimization factoring  
A workload scheduler supporting an efficient distribution and balancing of the workload is proposed. The scheduler maintains ( 383 - 386 ) a profile for each job; the profile (build using...
7287105 Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation  
Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer...
7260733 Distributed control system  
In a distributed control system, a first electronic control unit sends trigger information to a second electronic control unit. The trigger information includes a timing that triggers the second...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7251192 Register read for volatile memory  
Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read...
7219173 System for video processing control and scheduling wherein commands are unaffected by signal interrupts and schedule commands are transmitted at precise time  
A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of...
7215580 Non-volatile memory control  
According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of...
7206873 Throughput optimization by activation of selected parallel channels in a multichannel tape drive  
The present invention describes a method and system for adjusting the rate of data transfer between a high-speed multi-channel tape drive and a slower-capability network interface. The present...
7206233 Memory system with parallel data transfer between host, buffer and flash memory  
A memory system is provided which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and...
Matches 1 - 50 out of 307 1 2 3 4 5 6 7 >