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7624244 |
System for providing a slow command decode over an untrained high-speed interface
A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed...
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7624209 |
Method of and circuit for enabling variable latency data transfers
A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises...
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7617386 |
Scheduling thread upon ready signal set when port transfers data on trigger time activation
A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the...
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7617339 |
Serial interface circuit for data transfer
A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral...
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7610427 |
Functional module card for transferring digital broadcasting signal using a clock generated based on a synchronous signal extracted from a received data signal
A functional module card and a host apparatus according to the present invention can constitute the digital broadcasting receiver apparatus. The functional module card includes a card controller...
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7606955 |
Single wire bus for connecting devices and methods of operating the same
A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective...
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7606952 |
Method for operating serial flash memory
A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits...
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7603673 |
Method and system for reducing context switch times
An apparatus for managing resource in a multithreaded system, and attempting to increase the speed in which task switching occurs by controlling when thread state is stored to memory. The apparatus...
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7600053 |
Emulation of extended input/output measurement block facilities
An Extended Input/output (I/O) measurement block facility is emulated. The facility provides for the collection of relevant I/O measurement data, and the storing for later efficient retrieval of...
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7600049 |
Method, system, and computer program product for timing operations of different durations in a multi-processor, multi-control block environment
Operations in a multi-processor, multi-control block environment are timed using timing queues and instruction queues. Upon receipt of a request for a subchannel control block (SCB) to perform an...
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7596644 |
Transmit rate pacing system and method
System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace...
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7590789 |
Optimizing clock crossing and data path latency
In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct...
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7587533 |
Digital programming interface between a baseband processor and an integrated radio-frequency module
A circuit receives a clock signal, a data word which is emitted from a control device and has information about a read or write access to the circuit, and an enable signal which is at a...
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7587255 |
Software and process for play-cursor calculation
A process and software for achieving minimal latency in digital audio playback, which includes calculating a repeatable play cursor lead and a play cursor position and writing audio data at the...
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7567514 |
RAID apparatus, and communication-connection monitoring method and program
An interdevice communication monitoring unit 62 - 1 calculates a variable timeout time (T 2 −T) by subtracting an elapsed time T from a predetermined fixed timeout time T 2 for monitoring an...
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7565472 |
Host based automatic detection unit
There is provided several embodiments of the present invention, the invention being an automatic detection unit allowing for coupling of an external device with a host. The unit may connect to an...
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7565465 |
Pushback FIFO
The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a...
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7562185 |
Accessing a storage medium using dynamic read statistics
A method and system for accessing a storage medium that factors in read statistics of previous reads of the storage medium is provided. An access system tracks read statistics generated from...
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7552255 |
Dynamically partitioning pipeline resources
In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing...
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7552254 |
Associating address space identifiers with active contexts
In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space...
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7548998 |
Modifying host input/output (I/O) activity to allow a storage drive to which I/O activity is directed to access requested information
Provided are a method, system, and article of manufacture to process communications between a host and storage drive having a storage media. An Input/Output (I/O) request is received from the host...
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7548994 |
Disk initiated asynchronous event notification in an information handling system
A SAS target device, e.g., SAS disk, may instantiate an asynchronous event notification (AEN) transaction while still conforming to SAS protocol standards. When the SAS target has an event queued...
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7539793 |
Synchronized multichannel universal serial bus
The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
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7536489 |
Information processing system for determining payload size based on packet-to-payload size ratio
An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point...
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7533238 |
Method for limiting the size of a local storage of a processor
A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a...
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7516248 |
Obtaining extended queue measurement data for a range of logical control unit queues
I/O measurement data for channels attached to logical control unit queues is obtained related to a plurality of logical control unit queues. A store secondary queue measurement data instruction...
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7516247 |
Avoiding silent data corruption and data leakage in a virtual environment with multiple guests
In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed...
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7512766 |
Controlling preemptive work balancing in data storage
A storage network control apparatus is operable to present virtualized storage to a host system and includes a monitoring component, an analysis component, a detection component, and a migration...
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7512725 |
Generating a data stream from cartridge controllers using a plurality of measurement cartridges
System and method for controlling cartridges to perform industrial operation(s). The system may include cartridge controllers coupled to the cartridges, timing and data routing logic coupled to the...
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7509445 |
Adapting a plurality of measurement cartridges using cartridge controllers
System and method for controlling cartridges to perform industrial operation(s). The system may include cartridge controllers coupled to the cartridges, timing and data routing logic coupled to the...
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7506218 |
Timeout request scheduling using grouping and nonsynchronized processing to enhance performance
An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling...
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7502871 |
Method for query/modification of linear block address table entries for direct I/O
The present invention provides a method, that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local...
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7500042 |
Access control device for bus bridge circuit and method for controlling the same
An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an...
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7500031 |
Ring-based cache coherent bus
Managing data traffic among three or more bus agents configured in a topological ring includes numbering each bus agent sequentially and injecting messages that include a binary polarity value from...
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7490178 |
Threshold on unblocking a processing node that is blocked due data packet passing
A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the...
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7484214 |
Real time control system
A real-time control system for executing exactly a cyclic task, preventing a delay of the processing start time due to accumulation of a plurality of overhead times, thereby executing control...
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7484023 |
Computer system apparatus for stabilizing asynchronous interfaces
A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic,...
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7480846 |
Iterative turbo decoder with single memory
The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder ( 14 ) and a second decoder ( 16 ), each decoder being able to calculate extrinsic output data from...
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7480765 |
Storage unit and circuit for shaping communication signal
The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for...
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7467263 |
Storage system, management apparatus & method for determining a performance problem using past & current performance values of the resources
A highly-reliable system, a management apparatus and method that can enhance the reliability of a storage system is provided. The present invention provides a storage system having a higher level...
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7466608 |
Data input/output circuit having data inversion determination function and semiconductor memory device having the same
A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to...
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7464284 |
Systems and methods for driving data over a bus where the systems employ a bus clock that is derived from a system clock and a data clock designed to lead the bus clock
Systems and methods for driving data over a data bus are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing...
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7461186 |
Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements
The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a...
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7454589 |
Data buffer circuit, interface circuit and control method therefor
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
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7454539 |
Method for transferring variable isochronous data and apparatus therefore
A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous...
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7454538 |
Latency insensitive FIFO signaling protocol
Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further...
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7451246 |
Indirectly controlling a target device on a network
Methods and systems are described for a system for transitioning a target device to a first operative state, such as a service operating system. The target device in the first operative state then...
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7451070 |
Optimal bus operation performance in a logic simulation environment
Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator...
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7447805 |
Buffer chip and method for controlling one or more memory arrangements
A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received...
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7421692 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Real time control system
A real-time control system for executing exactly a cyclic task, preventing a delay of the processing start time due to accumulation of a plurality of overhead times, thereby executing control...
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