Matches 251 - 300 out of 503 < 1 2 3 4 5 6 7 8 9 10 11 >
Match Document Document Title
6457114 Asynchronous memory interface for a video processor with a 2N sized buffer and N&plus 1 wide bit gray coded counters  
A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for access...
6453372 Data communication system for and method of avoiding computer network transmissions of excessive length  
A data communication system includes in middleware a transmission task that transmits a message to a receiving host computer through a network, considering the transmission capability of the...
6452943 Data server system where the cycle for transmitting video or audio data is adjusted according to control data transmitted to a transmitter by a receiver that monitors its buffer state  
A video server system includes a transmitter for cyclically transmitting predetermined amounts of video data that have been read from a magnetic disc drive apparatus and a receiver for receiving...
6434642 FIFO memory system and method with improved determination of full and empty conditions and amount of data stored  
A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated...
6434692 High-throughput interface between a system memory controller and a peripheral device  
A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures....
6430652 Method and apparatus for streaming data in a data processing system  
An improved method and apparatus for transferring data in a CD-ROM system. The CD-ROM system includes a buffer manager for identifying the capacity of a buffer memory used to store data from a...
6418503 Buffer re-ordering system  
A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI...
6405256 Data streaming using caching servers with expandable buffers and adjustable rate of data transmission to absorb network congestion  
A data streaming transmission method and system is disclosed having a network server connected to client device through a communication network with one or more of caching servers. The network...
6405276 Selectively flushing buffered transactions in a bus bridge  
A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first...
6405269 FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers  
A comparator circuit for detecting full and empty conditions in a first-in first-out (FIFO) memory system. The comparator circuit includes two-input logic circuits for comparing selected read and...
6405283 Method for handling buffer under-run during disc recording  
Disclosed is a method for handling buffer under-runs during disc recording sessions on an optical disc. The method includes the operations of recording a volume descriptor sequence for the...
6401169 Optical disc buffer under-run handling method  
A method for handling buffer under-runs during the recording of files to an optical disc is provided. The method includes reserving a track for recording a file system associated with recording of...
6397287 Method and apparatus for dynamic bus request and burst-length control  
A network adapter is provided that controls the transfer of data between a host computer and a network medium in a manner which optimizes the amount of data transferred between the host computer...
6393514 Method of generating an almost full flag and a full flag in a content addressable memory  
An almost full flag is asserted when all but one of the rows of a CAM array contain valid data, as indicated by corresponding valid bits. In one embodiment, the almost full flag is generating using...
6393501 Microprocessor with external memory interface optimized by an early decode system  
A microprocessor circuit having an external memory interface includes a transmission element for the transmission of binary data packets between the microprocessor and the interface. The interface...
6389489 Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size  
A data processor ( 102 ) includes a first-in, first-out (FIFO) buffer ( 110 ) having a variable threshold. The FIFO buffer ( 110 ) has a plurality of entries ( 200 ) for storing at least a portion...
6380873 Method for reducing radio frequency emissions on high-speed serial buses  
A method for reducing radio frequency interference from a high frequency serial bus by scrambling data signals and reducing the repetition of control signals. Beginning and ending control signals...
6381659 Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses  
A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO...
6378057 Data processing apparatus  
The present invention relates to a data processing apparatus which allows a memory to be used as a line FIFO. A write port address modification information generating unit and a read port address...
6374313 FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased  
A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a...
6366968 Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails  
A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using...
6366984 Write combining buffer that supports snoop request  
A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second...
6363464 Redundant processor controlled system  
The operation of a shadow processor for a system having redundant controllers is arranged so that it receives a FIFO fill indicator from another shadow processor associated with that one of the...
6360286 Sequential data transfer with common clock signal for receiver and sequential storage device and with slack register storing overflow item when set-up time is insufficient  
The present invention provides a circuit for saving overflow data within a sequence of data that are to be clocked out of a sequential storage device. The sequential storage device has a data...
6351780 Network controller using held data frame monitor and decision logic for automatically engaging DMA data transfer when buffer overflow is anticipated  
A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of...
6345327 Queuing method and apparatus for providing direct data processing access using a queued direct input-output device  
A queuing method and apparatus for transfer or incoming and outgoing data in a network environment having a main storage is presented. A plurality of queue sets are provided in the main storage...
6343349 Memory caching for force feedback effects  
Methods and apparatus for efficient management of memory in a force feedback system including a host computer and a force feedback device. A representation of device memory is maintained on the...
6341326 Method and apparatus for data capture using latches, delays, parallelism, and synchronization  
A static random access memory device used in a system having a data clock includes a recirculating counter producing a pair of clocking signals and n data latches each connected to a source of data...
6338133 Measured, allocation of speculative branch instructions to processor execution units  
A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing...
6317809 Optical disk under-run protection using formatted padding sectors  
In an optical data storage device for storing data on a removable optical disk in a continuous sequence of sectors or blocks, the input data buffer may be subject to under-run. An under-run...
6314047 Low cost alternative to large dual port RAM  
Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory...
6304936 One-to-many bus bridge using independently and simultaneously selectable logical FIFOS  
A one-to-many bus bridge includes a system bus interface, a first I/O bus interface, a second I/O bus interface, a multiple logical FIFO system wherein first and second logical FIFOs share a common...
6304947 Optimized memory organization in a multi-channel architecture  
Described is a computer system having a multi-channel architecture wherein a plurality of individual channels, each having a respective channel memory and being connected by a bus. According to the...
6298387 System for detecting a data packet in a bitstream by storing data from the bitstream in a buffer and comparing data at different locations in the buffer to predetermined data  
Packets in a bitstream are delineated by a) employing a first in, first out buffer (FIFO) with a storage capacity equal to the number of bits in a packet plus the number of bits in the...
6289421 Intelligent memory devices for transferring data between electronic devices  
Intelligent memory devices allow for the transfer of data between two or more electronic devices, such as digital signal processors and microcontrollers. The memory devices may be designed as dual...
6286072 System and method for synchronizing data communication between asynchronous buses  
A synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency is provided. The...
6279065 Computer system with improved memory access  
A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge...
6279077 Bus interface buffer control in a microprocessor  
A microprocessor (5) including a plurality of write buffers (30) of varying sizes is disclosed. The varying sizes of the write buffers (30) allow for each write transaction from the core of the...
6275896 Data transfer apparatus and method of the same and data input and output controlling apparatus and method of same  
A data transfer apparatus for transferring data between a first storage medium and a second storage medium capable of non-linear access, comprising a temporary storing means for temporarily storing...
6272572 Apparatus and method for transmitting and receiving passenger service system and telephone signals over a network  
A system and method of distributing telephone and passenger service signals from a zone interface unit to a plurality of seat electronic units in an in-flight entertainment system is described. The...
6269413 System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections  
A multiple logical FIFO system uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system....
6266715 Universal serial bus controller with a direct memory access mode  
A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint...
6263410 Apparatus and method for asynchronous dual port FIFO  
An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f 2 <f 1 <f 2 or 0.5f 1 <f 2 ...
6253273 Lock mechanism  
A method of providing a lock to a requester, the method including the steps of storing a lock indicator at a storage location on a storage medium; receiving a lock command from a requester on a...
6246257 FIFO circuit  
A FIFO circuit with a reduced number of buffers connected to output ports and thereby lowering parasitic capacitance. The FIFO circuit includes an input register for storing data therein supplied...
6247072 Real-time data rate matching across a medium  
Apparatus and methods for matching data rates is useful for a receiver receiving real-time data over a medium. Implementations feature a process establishing a buffer in a receiver; receiving...
6247076 Data storing method and apparatus for storing data while effectively utilizing a small capacity of a memory  
A data storing apparatus includes a storing unit, an empty capacity detecting unit and a data deleting unit. The storing unit stores data. The empty capacity detecting unit detects an empty...
6243770 Method for determining status of multiple interlocking FIFO buffer structures based on the position of at least one pointer of each of the multiple FIFO buffers  
One embodiment of the present invention relates to a method for using at least two first-in, first-out ("FIFO") buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers,...
6233651 Programmable FIFO memory scheme  
A large FIFO memory device has its total available memory capacity partitioned into memory sections. The partitions are in the form of programmable delimiters in order to determine flexibly the...
6226698 Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO  
An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data...
Matches 251 - 300 out of 503 < 1 2 3 4 5 6 7 8 9 10 11 >