Matches 101 - 150 out of 503 < 1 2 3 4 5 6 7 8 9 10 11 >
Match Document Document Title
7093037 Generalized queue and specialized register configuration for coordinating communications between tightly coupled processors  
Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of...
7089380 Method and system to compute a status for a circular queue within a memory device  
A method and system are described to compute a status for a circular queue within a memory device. A head pointer and a tail pointer are maintained to identify a head entry and a tail entry,...
7088466 Print system and data transfer apparatus and method  
To efficiently transfer data from a host computer to a printer, a part of data developed in the first memory is outputted on the basis of a draw command to the printer, the data remaining in the...
7080169 Receiving data from interleaved multiple concurrent transactions in a FIFO memory having programmable buffer zones  
A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent...
7076545 Load balancing the servicing of received packets  
A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication...
7072998 Method and system for optimized FIFO full conduction control  
Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the...
7069356 Method of controlling a queue buffer by performing congestion notification and automatically adapting a threshold value  
A method of controlling a queue buffer ( 2 ), said queue buffer ( 2 ) being connected to a link ( 1 ) and being arranged to queue data units ( 30 ) that are to be sent over said link ( 1 ) in a...
7065623 Bandwidth utilization in a PPRC system  
Methods, system and computer program product are provided to improve the efficiency of data transfers in a PPRC environment. A block of data to be transferred is divided into tracks. Each track is...
7065628 Increasing memory access efficiency for packet applications  
Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily...
7058777 Microcontroller device for extending memory address by inserting a waiting state and the operation method for the device  
A microcontroller device for extending memory address space by inserting a waiting state and an operation method on the device. The device includes a CPU, a ROM, and a memory interface controller....
7054962 Embedded system having broadcast data storing controller  
An embedded system for receiving data packets from a communication network includes a plurality of buffers for storing data received from the communication network, and a pointer corresponding to...
7035983 System and method for facilitating communication across an asynchronous clock boundary  
A method includes storing data in one of a plurality of memory slots in a queue. Each memory slot is associated with a plurality of flags. The method also includes toggling a first of the flags...
7030849 Robust LCD controller  
An LCD controller ( 10 ) has a DMA unit ( 18 ) and a FIFO memory ( 20 ) for storing display data. The LCD controller also has a display data generator ( 26 ) that generates display information...
7028111 Bus system and bus interface for connection to a bus  
The invention relates to a bus system comprising a first station ( 202 ) and a second station ( 203 ), ( 204 ), coupled by a bus for transferring messages, said bus being designed to operate in...
7024499 Cache only queue option for cache controller  
A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are...
7007097 Method and system for covering multiple resourcces with a single credit in a computer system  
A method and system for communicating to a sender an availability of receiving a new message includes providing buffers having at least one corresponding slot for storing a message and providing a...
6996640 Method and system for asynchronously transferring data  
The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in...
6993602 Configuring queues based on a given parameter  
At least one queue parameter for a first process running on a system is determined. A queue management process separate from the first process configures one or more queues on a storage device in...
6993604 Dynamic buffer size allocation for multiplexed streaming  
A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a...
6993102 System and method for clock synchronization for USB sink device  
In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate...
6988160 Method and apparatus for efficient messaging between memories across a PCI bus  
The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as...
6988153 Data storing system and transmission control method  
The data storage system 1 comprises tape drives 21 to 23 operable to read and write data transmitted via the SCSI bus 112 from and on a tape in parallel and a host PC 4 for controlling...
6988122 Ferris-wheel queue  
The present invention provides a method of transferring incoming multithreaded concurrent sets of data from a sending transport system to a requesting transport system which includes retrieving the...
6985977 System and method for transferring data over a communication medium using double-buffering  
System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a...
6983350 SDRAM controller for parallel processor architecture  
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
6970962 Transfer request pipeline throttling  
A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N...
6961835 System and method for autonomically reallocating memory among buffer pools  
A system and method autonomically reallocate memory among buffer pools to permit quick access to data. A simulated buffer pool extension (SBPX) is created for each buffer pool in a set of buffer...
6957355 Method and system for dynamically adjusting storage system write cache based on the backup battery level  
A method and system for managing cache levels based on battery backup level are described. In one embodiment, the method comprises measuring the level of charge stored in an exhaustible power...
6954768 Method, system, and article of manufacture for managing storage pools  
Provided are a method, system, and article of manufacture for pooling of storage. Volume attributes are assigned to a plurality of physical volumes. Pool attributes are assigned to a plurality of...
6954831 Method, system, and article of manufacture for borrowing physical volumes  
Provided are a method, system, and article of manufacture for borrow processing in storage pools. A plurality of physical volumes are allocated to a first storage pool. A determination is made...
6950912 Memory manager for a common memory  
The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology...
6948030 FIFO memory system and method  
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic....
6944717 Cache buffer control apparatus and method using counters to determine status of cache buffer memory cells for writing and reading data therefrom  
Methods for controlling and storing data in a cache buffer in a storage apparatus having a nonvolatile memory medium are disclosed. Memory cells are logically divided into a plurality of pages. An...
6941426 System for head and tail caching  
A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail...
6941434 Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same  
An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in...
6934820 Traffic controller using priority and burst control for reducing access latency  
A memory traffic access controller ( 18 ) responsive to a plurality of requests to access a memory. The controller includes circuitry ( 18 d ) for associating, for each of the plurality of...
6931460 Dynamically self-adjusting polling mechanism  
A system and method is disclosed for preventing the loss of event messages due to message buffer overruns. A fixed vendor-specific buffer pool is loaded with log messages by firmware in an adapter....
6925508 Recording method from improving interrupted interference by checking size of main buffer and allocating alternative buffer to generating interpolated sample if main buffer is to small  
A recording method for improving interrupted interferences, for use in a recording apparatus. First, a buffer is allocated, and then, the size of the buffer is checked. If the size of the buffer is...
6920510 Time sharing a single port memory among a plurality of ports  
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in...
6918005 Method and apparatus for caching free memory cell pointers  
A method and apparatus are provided for caching free cell pointers pointing to memory buffers configured to store data traffic of network connections. In one example, the method stores free cell...
6907479 Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same  
Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a...
6907541 System for recovering received data with a reliable gapped clock signal after reading the data from memory using enable and local clock signals  
A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the...
6898664 Optimizing performance for a storage device within a computer system  
A data storage device may be constructed with a disk array; an array controller for controlling the array; and a queue for queuing commands from a host system to the disk array. Programming...
6892284 Dynamic memory allocation for assigning partitions to a logical port from two groups of un-assigned partitions based on two threshold values  
A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to...
6892253 Maintaining remote queue using two counters in transfer controller with hub and ports  
The data transfer apparatus and method employs two queue counters to maintain the status of a first-in-first-out buffer memory. A master count ( 251 ) indicates the number of entries available for...
6889270 Efficient reading of a remote first-in first-out buffer  
A method and system for a processor to efficiently accesses a remote First-in First-out (FIFO) buffer that is used to record event information. The access involves an interrupt mechanism when the...
6882656 Speculative transmit for system area network latency reduction  
A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit...
6877049 Integrated FIFO memory management control system using a credit value  
An integrated data controller that utilizes a first-in first-out (FIFO) management system that compensates for the unpredictable nature of latency associated with requesting data from memory and...
6874043 Data buffer  
A direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data...
6865638 Apparatus and method for transferring multi-byte words in a fly-by DMA operation  
An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner...
Matches 101 - 150 out of 503 < 1 2 3 4 5 6 7 8 9 10 11 >