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7366803 |
Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty
A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data...
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7366804 |
Programmatic time-gap defect correction apparatus and method
A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers,...
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7366801 |
Method for buffering work requests
Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing...
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7363412 |
Interrupting a microprocessor after a data transmission is complete
A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with...
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7362771 |
Reduced latency FIFO
A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to...
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7363395 |
Intermediate device capable of communicating using different communication protocols
A method according to one embodiment may include determining, at least in part, by an intermediate device at least one communication protocol via which at least one storage device connected to the...
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7356624 |
Interface between different clock rate components
A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than...
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7353298 |
Data transfer processing method
Processing which, in conventional data transfer processing, entails the use of the common bus when performing (1) processing to confirm the interrupt state, performed via the common bus employing...
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7353356 |
High speed, low current consumption FIFO circuit
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
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7337248 |
Adaptive synchronization method for communication in storage systems
A method for transferring data in a storage system is provided. The method includes setting a catch-up threshold for accepting data requests from a port where the queue value corresponds to a...
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7334063 |
Method and device for register access according to identifier register
A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a...
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7321554 |
Method and apparatus for preventing blocking in a quality of service switch
A method, apparatus, and computer-readable media for sending a frame of data from a first channel to a second channel using at least one of m memory buffers for storing a frame, m being at least 2,...
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7320042 |
Dynamic network interface
A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the...
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7316234 |
Medical imaging installation and operating method for reading stored signals to reconstruct a three-dimensional image of a subject
In a method for operating a medical imaging installation, at least one sensor detects measured signals from an object and supplies them to a control device that buffer-stores the measured signals...
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7302503 |
Memory access engine having multi-level command structure
A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each...
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7296193 |
Technique for processing an error using write-to-operator-with-reply in a ported application
A method, apparatus and article of manufacture, implementing the method, processes an error when a write fails in an application that has been ported from a first platform to a second platform. The...
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7287106 |
Regulating real-time data capture rates to match processor-bound data consumption rates
Subject matter to regulate real-time data capture rates to match processor-bounded data consumption operations is described. In one aspect, a computing device receives data from a data source at a...
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7287107 |
Method and apparatus for passive PCI throttling in a remote server management controller
The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop...
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7284075 |
Inbound packet placement in host memory
Provided is a method, system, and article of manufacture for inbound packet placement in host memory. A first packet for a buffer in memory is received and a descriptor is generated indicating a...
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7284074 |
Pipelined network processing with FIFO queues
A system and method for operating on data within a network device is described. Between two data operations in a network device is a FIFO queue, which is used to separate the clock domains of the...
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7281077 |
Elastic buffer module for PCI express devices
A method and system for a PCI Express device is provided. The elastic buffer includes, a buffer control module that determines a difference between a write and read pointer value and compares the...
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7272672 |
High speed bus with flow control and extended burst enhancements between sender and receiver wherein counter is maintained at sender for free buffer space available
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described.
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7269700 |
Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system
A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory...
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7257665 |
Branch-aware FIFO for interprocessor data sharing
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations...
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7257687 |
Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system
A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to...
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7254595 |
Method and apparatus for storage and retrieval of very large databases using a direct pipe
A method and apparatus for directly connecting very large data streams from an archive command into a backup data system using an “intelligent process.” An output stream is piped into an...
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7254677 |
First-in, first-out memory system with reduced cycle latency
A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the...
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7251702 |
Network controller and method of controlling transmitting and receiving buffers of the same
In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from...
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7249237 |
Control method for data transfer control unit
An upper-level host has a control unit and a host controller for controlling the operation of a device. The host controller includes a buffer memory that reads data from the device into the buffer...
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7249206 |
Dynamic memory allocation between inbound and outbound buffers in a protocol handler
An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the...
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7239645 |
Method and apparatus for managing payload buffer segments in a networking device
A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is...
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7240130 |
Method of transmitting data through an 12C router
A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing...
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7237131 |
Transaction-based power management in a computer system
A method and an apparatus for power management in a computer system have been disclosed. One embodiment of the method includes monitoring transactions over an interconnect coupling a chipset device...
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7219171 |
Flow control for digital signal processing to support data stream operations
A method and apparatus are described for flow control for digital signal processing to support data stream operations. According to an embodiment of the invention, a method comprises setting a...
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7213094 |
Method and apparatus for managing buffers in PCI bridges
Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a...
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7206871 |
Extending circuit for memory and transmitting-receiving device using extending circuit for memory
An extending circuit for memory includes an output data effective signal generator for, when a status signal from a next-stage FIFO circuit represents a data writable state, asserting a write...
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7203776 |
Method of data transmission and a transmission and reception device therefor
A data transmission method and a transmission/reception device are described, the data transmission taking place via intermediate memories without the transmitter receiving direct feedback from the...
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7203803 |
Overflow protected first-in first-out architecture
An electronic device ( 10 ). The device comprises an input ( 16 I ) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The...
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7203775 |
System and method for avoiding deadlock
A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that...
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7197582 |
Low latency FIFO circuit for mixed clock systems
A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The...
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7191162 |
FIFO interface for flag-initiated DMA frame synchro-burst operation
The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an...
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7185125 |
Device for transferring data via write or read pointers between two asynchronous subsystems having a buffer memory and plurality of shadow registers
Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer...
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7177963 |
System and method for low-overhead monitoring of transmit queue empty status
A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of...
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7165129 |
Method and apparatus for self-tuning transaction batching
In a transaction system, a dynamic batching process enables efficient flushing of data in a data buffer to a stable storage device. The transaction system uses constant values and dynamic values...
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7159051 |
Free packet buffer allocation
According to some embodiments, systems an apparatuses may have a communication path to exchange information packets. A processor may process information packets. A buffer pool cache local to the...
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7154984 |
FIFO-register and digital signal processor comprising a FIFO-register
A FIFO-register ( 10 ) according to the invention comprises a sequence of register cells ( 10.1, . . . ,10 .m), which register cells have a data section ( 40 ) and a status section ( 30 ). Data...
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7139884 |
Method, apparatus and computer program product for implementing enhanced autonomic backup using multiple backup devices
A method, apparatus and computer program product are provided for implementing enhanced autonomic data backup using multiple backup devices. A media definition object is defined for saving...
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7130937 |
Method for providing a video data streaming service
In a method for providing a video data streaming service, a server determines whether an occupancy is below a first threshold or is equal to or greater than a second threshold, the occupancy...
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7117287 |
History FIFO with bypass wherein an order through queue is maintained irrespective of retrieval of data
An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The...
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7099972 |
Preemptive round robin arbiter
A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for...
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