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7624206 |
RAID data storage system with SAS expansion
A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator...
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7603498 |
System and method for managing multiple information handling systems using embedded control logic
A system and method for managing multiple information handling systems using embedded control logic are disclosed. An information handling system includes a first port for receiving first analog...
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7590776 |
Data storage techniques utilizing host-side multiplexers
A data storage system has a circuit board module, a set of Serial ATA devices, and a set of Serial ATA cables connecting the circuit board module to the set of Serial ATA devices. The circuit board...
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7574542 |
SAS expansion topology for RAID data storage including multiplexers and SAS expanders for interfacing with single or dual ports drives
A data storage system having a first chassis, such first chassis having a pair of SAS expanders and a second chassis having a pair of SAS expanders. The first one of the pair of SAS expanders is...
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7571271 |
Lane merging
A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers...
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7509444 |
Data access device for working with a computer of power off status
This invention discloses a data access device for using in computer of power off status, which comprises a power multiplexer, a DC to DC converter, a serial bus signal to storage interface signal...
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7493421 |
Media sharing apparatus, system, and method for enabling computing devices to share a drive
A media sharing apparatus includes a plurality of connecting ports for connecting with a plurality of computing devices. A KVM switch connecting with a drive is coupled to the media sharing...
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7472210 |
Multiplexing and bypass circuit for interfacing either single or dual ported drives to multiple storage processors
Single and dual ported devices are interfaced to a system via a 2:2 multiplexing device. The multiplexing device is coupled to two system ports and two device ports. The multiplexing device...
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7469307 |
Storage system with DMA controller which controls multiplex communication protocol
A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer...
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7461186 |
Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements
The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a...
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7454535 |
Bidirectional data repeater switch
A bidirectional repeater and data multiplexer for serial data has A-side I2C port devices A 1 -A 4 coupled to comparators 302 - 308 and pulldowns to ground 316 - 322 . Comparator outputs are...
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7437491 |
Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM
Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on...
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7412546 |
System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The...
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7398334 |
Circuit for and method of realigning data
A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data...
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7376956 |
System for performing multiple functions in parallel time
A architecture for a multifunction peripheral to service a plurality of clients simultaneously. A shared memory receives data from the plurality of clients. A channel multiplexer selects data to be...
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RE40317 |
System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer
A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component...
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7368939 |
Data input/output circuit included in semiconductor memory device
A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input...
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7352372 |
Indirect addressing mode for display controller
A display controller is provided. The display controller is configured to provide an indirect addressing mode to access a memory location within the display controller. The display controller...
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7333580 |
Pipelined parallel processing of feedback loops in a digital circuit
Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A...
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7281066 |
Memory access system including support for multiple bus widths
A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second...
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7254653 |
Switch control system and method that distinguishes between a plurality of real and emulated input devices
A switch control system has a switch device for selecting a real input device or an emulation input device, an instruction detecting device electrically connected to a computer system and the...
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7254647 |
Network for decreasing transmit link layer core speed
A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core...
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7251280 |
Circuit structure and signal encoding method for a serial ATA external physical layer
A circuit structure and signal encoding method for a serial ATA external physical layer is provided. The circuit structure and signal encoding method thereof is capable of reducing the number of...
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7249167 |
Intelligent modular server management system for selectively operating a plurality of computers
An intelligent, modular server management system for coupling a series of remotely located computers to one or more user stations allowing for selective access of the remotely located computers. A...
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7219171 |
Flow control for digital signal processing to support data stream operations
A method and apparatus are described for flow control for digital signal processing to support data stream operations. According to an embodiment of the invention, a method comprises setting a...
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7200691 |
System and method for efficient DMA transfer and buffering of captured data events from a nondeterministic data bus
A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system...
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7191257 |
System and method for real-time processing of nondeterministic captured data events
A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a...
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7185125 |
Device for transferring data via write or read pointers between two asynchronous subsystems having a buffer memory and plurality of shadow registers
Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer...
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7143226 |
Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link
The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various...
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7143216 |
System for configuring expandable buses in a multi-device storage container and related method
A system and method for configuring expandable buses wherein a host supports a plurality of expandable buses are provided. A plurality of devices are arranged to form a plurality of groups. Each...
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7124213 |
Device having spare I/O and method of using a device having spare I/O
A method and apparatus for correcting internally defective devices by routing signals on an I/O line to a spare internal network. Such devices enable a system designer to substitute good internal...
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7085861 |
Serial ATA control circuit for automatically switching connection path
A serial ATA control circuit is provided. The control circuit includes a plurality of serial ATA controllers, a plurality of port controlling circuits, a plurality of switch devices, and a switch...
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7085858 |
Configuration in a configurable system on a chip
The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The...
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7069363 |
On-chip bus
A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive...
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7016988 |
Output buffer register, electronic circuit and method for delivering signals using same
An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N...
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7000059 |
Integrated PCI interface card and bus system thereof
The present invention discloses an integrated PCI interface card and the bus system thereof. The integrated PCI interface card of the present invention includes at least two bus masters, a control...
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6988268 |
IO completion architecture for user-mode networking
A new method and framework for implementing network protocol processing utilizing a combination of application threads and a dedicated thread to process IO completions in a completion queue that...
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6970967 |
Crossbar circuit having a plurality of repeaters forming different repeater arrangements
A crossbar circuit ( 30, 40, 50, 60, 70, 80, 90, 100 ) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A...
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6968418 |
Data forwarding by host/PCI-X bridges with buffered packet size determined using system information
Embodiments are provided in which a method is described for transferring data in a digital system comprising a first bus, a second bus, and a bridge coupling the first and second buses. During...
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6961792 |
System for configuring expandable buses in a multi-device storage container and related method
A system and method for configuring expandable buses wherein a host supports a plurality of expandable buses are provided. A plurality of devices are arranged to form a plurality of groups. Each...
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6948023 |
Transmission interface conversion device
The present invention provides a transmission interface conversion device, which can first convert the communication signal of a master equipment controller and then connect to a plurality of slave...
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6924746 |
Device and method to establish temporal correspondence in multiple sensor configurations
A sensor concentrating system centralizes communication between multiple parameter sensing devices and an application host. As a peripheral device, the sensor concentrating unit establishes a...
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6920510 |
Time sharing a single port memory among a plurality of ports
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in...
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6915367 |
Shared peripheral architecture
A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor...
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6907479 |
Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same
Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a...
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6826637 |
Implementing for buffering devices in circuit layout to ensure same arriving time for clock signal from source root to output bonding pads
An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which...
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6782435 |
Device for spatially and temporally reordering for data between a processor, memory and peripherals
A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from...
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6779092 |
Reordering requests for access to subdivided resource
One embodiment comprises an apparatus for reordering requests for access to a subdivided resource. The apparatus includes a non-FIFO request buffer for temporarily storing the requests for access,...
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6775719 |
Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in a data network
A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged...
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6742058 |
Memory controller having a multiplexer selecting either second set of input signals or converted signals from first set of input signals by a bus mode input
A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory...
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