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8838848 Systems and methods for intelligent system profile unique data management  
Systems and methods are provided that may be implemented to manage machine-specific System Profile Unique Data (SPUD) information for one or more information handling systems. Such SPUD information...
8762599 Delegating a poll operation to another device  
In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect...
8683100 Method and apparatus for handling data flow in a multi-chip environment using an interchip interface  
A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign...
8539485 Polling using reservation mechanism  
A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a...
8522355 System and method to force a mobile device into a secure state  
Embodiments relate to systems and methods for implementation on a mobile device to force the mobile device into a secure state upon detection or determination of a triggering event. Once it is...
8473657 High speed packet FIFO output buffers for switch fabric with speedup  
Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives...
8458426 Transceiver with latency alignment circuitry  
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface...
8423681 Control apparatus for process input-output device  
A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal...
8417849 Apparatus and method to adjust a multi-path device reservation  
A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage...
8368912 Image forming apparatus, print control method, and computer-readable storage medium storing program code for executing the control method  
An image forming apparatus capable of both normal printing and special-purpose printing includes a first identification unit, a second identification unit, and a selection unit. The first...
8332549 Method and system for implementing parallelism with SCSI I/O referrals  
A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include...
8296489 Priority control device  
A priority control device comprises a clock generator for generating a clock signal, a time interval generating unit having a plurality of signal routes and each of the signal routes has a...
8275938 Computer system for controlling allocation of physical links and method thereof  
The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of...
8270335 Arbitration for time division multiple access using delta sigma modulation  
Method and device for arbitration for time division multiple access using delta-sigma modulation for an integrated circuit are described. A method for arbitrating access to a shared resource among...
8205024 Protecting ownership transfer with non-uniform protection windows  
In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request....
8190803 Hierarchical bus structure and memory access protocol for multiprocessor systems  
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus...
8190829 Data processing circuit with multiplexed memory  
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can...
8190783 Assigning input devices to specific sessions  
Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the...
8135554 Probe configuration data protocol and transmission method  
Transmission of probe configuration data is initiated upon recognition by the probe of a prescribed condition. Probe configuration data protocol includes a data frame, subdivided into a desired...
8095695 Control apparatus for process input-output device  
A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal...
8086812 Transceiver with latency alignment circuitry  
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface...
8086770 Communication apparatus with data discard functions and control method therefor  
In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard...
7962673 Method and apparatus for accessing a data bus to transfer data over the data bus  
A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from...
7945727 Disk drive refreshing zones in segments to sustain target throughput of host commands  
A disk drive is disclosed including a disk comprising a plurality of refresh zones, and a head actuated over the disk. The disk drive further comprises control circuitry for receiving access...
7920882 Human interface device and wireless communication method thereof  
Provided are a human interface device and a wireless communication method thereof. The wireless communication method of the human interface includes the steps of: setting up an occupancy channel of...
7913011 Method and apparatus for employing a second bus controller on a data bus having a first bus controller  
A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting...
7913037 Computer system for controlling allocation of physical links and method thereof  
The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of...
7818479 Interface apparatus and packet transfer method  
A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a...
7809872 Master and slave device for communicating on a communication link with limited resource  
A master device for communicating with a number of slave devices through a communication link having a limited resource. The master device comprises a transceiver adapted for communicating with the...
7757019 Mobile hub and managing events in a mobile hub  
A mobile hub is proposed, the mobile hub includes a circular buffer for storing events, a timer for monitoring the storage period of an event stored in the buffer, and an event manager designed for...
7680966 Memory interface including generation of timing signals for memory operation  
A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link...
7587530 Method and apparatus for managing device reservation  
Methods and apparatus are disclosed for managing device reservation. In one embodiment, upon receiving a device command from a first host, a device targeted by the device command is reserved for...
7512724 Multi-thread peripheral processing using dedicated peripheral bus  
One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a...
7487300 Data processing circuit with multiplexed memory  
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can...
7483897 System and method for harvesting of data from peripheral devices  
A system and method harvest data from at least one device, by canvassing the devices and tracking which canvassed devices yielded harvested data and then repeating such canvassing and tracking...
7421521 System, method and device for real time control of processor  
A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may,...
7373438 System and method for reprioritizing high-latency input/output operations  
A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by...
RE40261 Apparatus and method of partially transferring data through bus and bus master control device  
A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data...
7340545 Distributed peer-to-peer communication for interconnect busses of a computer system  
There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to...
7299308 Data transmission apparatus and electronic control unit  
An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in...
7263573 Wireless USB hardware scheduling  
In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high...
7191273 Method and apparatus for scheduling a resource to meet quality-of-service restrictions  
The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first...
7185123 Method and apparatus for allocating bandwidth on a transmit channel of a bus  
A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending...
7146439 Management of background copy task for point-in-time copies  
A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and...
7139860 On chip network with independent logical and physical layers  
An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket...
7124270 Transceiver with latency alignment circuitry  
A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path...
7093256 Method and apparatus for scheduling real-time and non-real-time access to a shared resource  
A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time...
7076573 Method, apparatus, and program for detecting sequential and distributed path errors in MPIO  
An error detection mechanism is provided for detecting sequential and distributed errors in a device I/O stream. The sensitivity of the errors is user definable. The result of the error detection...
7072996 System and method of transferring data between a processing engine and a plurality of bus types using an arbiter  
A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a...
7065622 Transceiver with latency alignment circuitry  
A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through...
Matches 1 - 50 out of 143 1 2 3 >