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7587530 Method and apparatus for managing device reservation  
Methods and apparatus are disclosed for managing device reservation. In one embodiment, upon receiving a device command from a first host, a device targeted by the device command is reserved for...
7512724 Multi-thread peripheral processing using dedicated peripheral bus  
One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a...
7487300 Data processing circuit with multiplexed memory  
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can...
7483897 System and method for harvesting of data from peripheral devices  
A system and method harvest data from at least one device, by canvassing the devices and tracking which canvassed devices yielded harvested data and then repeating such canvassing and tracking...
7421521 System, method and device for real time control of processor  
A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may,...
7373438 System and method for reprioritizing high-latency input/output operations  
A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by...
RE40261 Apparatus and method of partially transferring data through bus and bus master control device  
A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data...
7340545 Distributed peer-to-peer communication for interconnect busses of a computer system  
There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to...
7299308 Data transmission apparatus and electronic control unit  
An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in...
7263573 Wireless USB hardware scheduling  
In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high...
7191273 Method and apparatus for scheduling a resource to meet quality-of-service restrictions  
The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first...
7185123 Method and apparatus for allocating bandwidth on a transmit channel of a bus  
A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending...
7146439 Management of background copy task for point-in-time copies  
A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and...
7139860 On chip network with independent logical and physical layers  
An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket...
7124270 Transceiver with latency alignment circuitry  
A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path...
7093256 Method and apparatus for scheduling real-time and non-real-time access to a shared resource  
A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time...
7076573 Method, apparatus, and program for detecting sequential and distributed path errors in MPIO  
An error detection mechanism is provided for detecting sequential and distributed errors in a device I/O stream. The sensitivity of the errors is user definable. The result of the error detection...
7072996 System and method of transferring data between a processing engine and a plurality of bus types using an arbiter  
A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a...
7065622 Transceiver with latency alignment circuitry  
A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through...
7065596 Method and apparatus to resolve instruction starvation  
Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a...
7028118 Multi-channel buffered serial port debugging  
In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The...
7010658 Transceiver with latency alignment circuitry  
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface...
6970986 Software based system and method for I/O chip hiding of processor based controllers from operating system  
An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An...
6965966 Disk drive pre-computing seek parameters for a continuation track and a next command to facilitate continuing a read-ahead or aborting the read-ahead  
A disk drive is disclosed which pre-computes first seek parameters to seek to a continuation track storing read-ahead data, and second seek parameters to seek to a target track of a next command....
6965961 Queue-based spin lock with timeout  
A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other...
6920510 Time sharing a single port memory among a plurality of ports  
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in...
6898649 Arbiter for queue management system for allocating bus mastership as a percentage of total bus time  
An arbiter ( 7 ) is provided for a QMS having multiple queue users ( 5 A to 5 D), each having real time requirements for mastership of a bus ( 31 ). The arbiter ( 7 ) is arranged so that the...
6868486 Providing multiple memory controllers on a memory bus  
A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority...
6834315 Method, system, and program for prioritizing input/output (I/O) requests submitted to a device driver  
Provided is a method, system, and program for managing Input/Output (I/O) requests generated by an application program. The I/O requests are transmitted to an output device. A determination is made...
6816928 Packet communication apparatus with first and second processing circuits which access a storage circuit during first and second time periods, respectively  
A packet communication apparatus processes consecutively transmitted fixed-length packets. The apparatus includes a storage circuit, a first processing circuit which accesses the storage circuit...
6813673 Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation  
In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an...
6813654 Data processing apparatus having a flow control function for multi-cast transfer  
Two transfer modes of a band-guaranteed cycle and an event-driven type asynchronous cycle are defined for a multimedia bus. In the band-guaranteed cycle, stream data is transferred between nodes,...
6769038 Method and apparatus for a wearable computer  
A wearable computer system includes a processing unit ( 102 ) and a number of peripherals. The processing unit and peripherals are coupled in a daisy-chain fashion utilizing a serial bus ( 120 )....
6763439 Disk throttling and priority queuing for streaming I/O  
A system is configured to prioritize streaming disk I/O over non-streaming disk I/O by providing high priority queuing to streaming disk I/O and/or to throttle non-streaming disk I/O when the total...
6757754 Data transfer unit for receiving general purpose commands when no expedited command is arriving  
A data transfer unit is provided which reliably receives the expedited command when the expedited command has arrived, and changes over the reception to receiving a general purpose command when no...
6745302 Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array  
A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and...
6732196 Allowing slots belonging to a second slot category to receive I/O access requests belonging to a first and a second access request categories in a round robin fashion  
A method for dispatching input/output access requests to a direct access storage device (DASD) is disclosed. Each of a group of I/O access requests to DASD is assigned into one of at least two I/O...
6721813 Computer system implementing a system and method for tracking the progress of posted write transactions  
A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem...
6715006 Disk time-sharing apparatus and method  
An input/output scheduling unit forms input/output groups obtained by grouping inputs/outputs to/from a disk apparatus. The input/output scheduling unit defines a ratio of the time during which...
6675268 Method and apparatus for handling transfers of data volumes between controllers in a storage environment having multiple paths to the data volumes  
In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array...
6609165 Method and apparatus for using fibre channel extended link service commands in a point-to-point configuration  
The present invention provides fibre channel networks the ability to use extended link service commands, previously confined to networks including a fabric controller, in a direct attach,...
6609163 Multi-channel serial port with programmable features  
A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120 . MCSP 120 includes clock generation and frame sync generation circuitry 300 , multi-channel selection...
6587932 Processor and system for controlling shared access to a memory  
Several peripheral entities, each of which is clocked by its own internal clock signal, can access a memory that is a single-access memory. A priority entity is defined from among the peripheral...
6530000 Methods and systems for arbitrating access to a disk controller buffer memory by allocating various amounts of times to different accessing units  
A method and system for arbitrating access to a shared disk controller resource, including a buffer memory of a hard disk controller (HDC). An access cycle with a first cycle duration are disclosed...
6499066 Method and apparatus for using fibre channel test extended link service commands for interprocess communication  
The present invention provides fiber channel networks the ability to use extended link service commands to convey implementation dependent information between ports.
6480904 Disk-time-sharing apparatus and method  
A disk time-sharing apparatus is constructed by a disk apparatus having disk drives, an input/output request unit for issuing an input/output request to the disk apparatus, and an input/output...
6434638 Arbitration protocol for peer-to-peer communication in synchronous systems  
An arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware...
6430606 High speed signaling for interfacing VLSI CMOS circuits  
A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate...
6418538 Method and system for scheduling transactions over a half duplex link  
Transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods....
6363440 Method and apparatus for buffering an incoming information signal for subsequent recording  
A method and system for storing an information signal for subsequent recording are disclosed. An incoming information signal is received, and a starting point in the information signal is...
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