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8423681 |
Control apparatus for process input-output device
A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal...
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8417849 |
Apparatus and method to adjust a multi-path device reservation
A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage...
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8368912 |
Image forming apparatus, print control method, and computer-readable storage medium storing program code for executing the control method
An image forming apparatus capable of both normal printing and special-purpose printing includes a first identification unit, a second identification unit, and a selection unit. The first...
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8332549 |
Method and system for implementing parallelism with SCSI I/O referrals
A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include...
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8296489 |
Priority control device
A priority control device comprises a clock generator for generating a clock signal, a time interval generating unit having a plurality of signal routes and each of the signal routes has a...
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8275938 |
Computer system for controlling allocation of physical links and method thereof
The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of...
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8270335 |
Arbitration for time division multiple access using delta sigma modulation
Method and device for arbitration for time division multiple access using delta-sigma modulation for an integrated circuit are described. A method for arbitrating access to a shared resource among...
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8205024 |
Protecting ownership transfer with non-uniform protection windows
In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request....
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8190803 |
Hierarchical bus structure and memory access protocol for multiprocessor systems
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus...
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8190829 |
Data processing circuit with multiplexed memory
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can...
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8190783 |
Assigning input devices to specific sessions
Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the...
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8135554 |
Probe configuration data protocol and transmission method
Transmission of probe configuration data is initiated upon recognition by the probe of a prescribed condition. Probe configuration data protocol includes a data frame, subdivided into a desired...
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8095695 |
Control apparatus for process input-output device
A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal...
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8086812 |
Transceiver with latency alignment circuitry
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface...
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8086770 |
Communication apparatus with data discard functions and control method therefor
In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard...
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7962673 |
Method and apparatus for accessing a data bus to transfer data over the data bus
A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from...
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7945727 |
Disk drive refreshing zones in segments to sustain target throughput of host commands
A disk drive is disclosed including a disk comprising a plurality of refresh zones, and a head actuated over the disk. The disk drive further comprises control circuitry for receiving access...
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7920882 |
Human interface device and wireless communication method thereof
Provided are a human interface device and a wireless communication method thereof. The wireless communication method of the human interface includes the steps of: setting up an occupancy channel of...
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7913011 |
Method and apparatus for employing a second bus controller on a data bus having a first bus controller
A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting...
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7913037 |
Computer system for controlling allocation of physical links and method thereof
The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of...
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7818479 |
Interface apparatus and packet transfer method
A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a...
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7809872 |
Master and slave device for communicating on a communication link with limited resource
A master device for communicating with a number of slave devices through a communication link having a limited resource. The master device comprises a transceiver adapted for communicating with the...
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7757019 |
Mobile hub and managing events in a mobile hub
A mobile hub is proposed, the mobile hub includes a circular buffer for storing events, a timer for monitoring the storage period of an event stored in the buffer, and an event manager designed for...
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7680966 |
Memory interface including generation of timing signals for memory operation
A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link...
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7587530 |
Method and apparatus for managing device reservation
Methods and apparatus are disclosed for managing device reservation. In one embodiment, upon receiving a device command from a first host, a device targeted by the device command is reserved for...
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7512724 |
Multi-thread peripheral processing using dedicated peripheral bus
One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a...
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7487300 |
Data processing circuit with multiplexed memory
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can...
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7483897 |
System and method for harvesting of data from peripheral devices
A system and method harvest data from at least one device, by canvassing the devices and tracking which canvassed devices yielded harvested data and then repeating such canvassing and tracking...
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7421521 |
System, method and device for real time control of processor
A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may,...
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7373438 |
System and method for reprioritizing high-latency input/output operations
A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by...
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RE40261 |
Apparatus and method of partially transferring data through bus and bus master control device
A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data...
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7340545 |
Distributed peer-to-peer communication for interconnect busses of a computer system
There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to...
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7299308 |
Data transmission apparatus and electronic control unit
An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in...
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7263573 |
Wireless USB hardware scheduling
In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high...
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7191273 |
Method and apparatus for scheduling a resource to meet quality-of-service restrictions
The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first...
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7185123 |
Method and apparatus for allocating bandwidth on a transmit channel of a bus
A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending...
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7146439 |
Management of background copy task for point-in-time copies
A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and...
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7139860 |
On chip network with independent logical and physical layers
An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket...
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7124270 |
Transceiver with latency alignment circuitry
A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path...
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7093256 |
Method and apparatus for scheduling real-time and non-real-time access to a shared resource
A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time...
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7076573 |
Method, apparatus, and program for detecting sequential and distributed path errors in MPIO
An error detection mechanism is provided for detecting sequential and distributed errors in a device I/O stream. The sensitivity of the errors is user definable. The result of the error detection...
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7072996 |
System and method of transferring data between a processing engine and a plurality of bus types using an arbiter
A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a...
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7065622 |
Transceiver with latency alignment circuitry
A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through...
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7065596 |
Method and apparatus to resolve instruction starvation
Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a...
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7028118 |
Multi-channel buffered serial port debugging
In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The...
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6970986 |
Software based system and method for I/O chip hiding of processor based controllers from operating system
An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An...
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6965966 |
Disk drive pre-computing seek parameters for a continuation track and a next command to facilitate continuing a read-ahead or aborting the read-ahead
A disk drive is disclosed which pre-computes first seek parameters to seek to a continuation track storing read-ahead data, and second seek parameters to seek to a target track of a next command....
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6965961 |
Queue-based spin lock with timeout
A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other...
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6920510 |
Time sharing a single port memory among a plurality of ports
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in...
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6898649 |
Arbiter for queue management system for allocating bus mastership as a percentage of total bus time
An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time...
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