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7617331 System and method of double address detection  
A plurality of detectors can be evaluated to determine if more than one has been assigned the same address. Responsive thereto, such detectors could be identified for follow-up maintenance, or...
7610063 System for determining information for circuit packs connected by a single line bus  
A system for determining slot specific information in a base station includes a switch provided in connection with each circuit pack in slots of the base station. The switches are selectively...
7606943 Adaptable datapath for a digital processing system  
The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN...
7587535 Data transfer control device including endian conversion circuit with data realignment  
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
7574536 Routing direct memory access requests using doorbell addresses  
An infrastructure element can receive a first DMA request including a first address and the data, generate a meta request that comprises a resource key value and a doorbell address, and transmit...
7567471 High speed fanned out system architecture and input/output circuits for non-volatile memory  
In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of...
7565463 Scalable routing and addressing  
PCI Express transactions can be transmitted via a shared PCI Express infrastructure. At an infrastructure ingress point an additional header comprising at least a source identifier and a target...
7565460 Information processing apparatus and method for handling packet streams  
A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the...
7558821 Process for assigning addresses in a network, and components for said process  
A process is proposed for the automatic assignment of at least one client device address in a DP network, where the DP network comprises a server device and at least one client device and where the...
7555568 Method and apparatus for operating a host computer from a portable apparatus  
The present invention provides methods and apparatus that utilize a portable apparatus to operate a host computer. The portable apparatus including an operating system and a list of software...
7533216 Device and method for simulating a hard disk  
A device and a method for simulating a hard disk are disclosed. The device has a core logic chip, a main memory module and a setting module. The setting module is used to set the main memory module...
7526596 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Methods and systems for an identifier-based memory section  
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
7526017 Transmitting device, receiving device, transmission system, and transmission method  
A transmitter LSI 1 transmits a source clock, transmission data, and a transmission sync signal indicating the timing of the transmission data to a receiver LSI for establishing transmission...
7523245 Compact ISA-bus interface  
An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral...
7523226 Controlling an auxiliary display user interface based on usage context  
An auxiliary computing device normally used for remotely controlling a primary device may change its functionality and extend its usefulness based on a usage context. An auxiliary device may change...
7519696 Method and apparatus for dynamically modifying a computer system configuration  
One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least...
7502876 Background memory manager that determines if data structures fits in memory with memory state transactions map  
A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map...
7477648 Packet forwarding apparatus and access network system  
An access network system connected to an ISP network including a subscriber authentication server comprised of a plurality of packet forwarding apparatuses each for connecting user terminals to an...
7461180 Method and apparatus for synchronizing use of buffer descriptor entries for shared data packets in memory  
Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned...
7444440 Method and device for providing high data rate for a serial peripheral interface  
An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial...
7444437 Input/output device and method of setting up identification information in input/output device  
An input/output device and a method of setting up identification information for an input/output device, to confirm which slot of which device enclosure each unit is mounted in, within a short...
7426607 Memory system and method of operating memory system  
A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of...
7408661 Control apparatus and its method, and control program and storage medium holding it, with access designating second address being performed based on link to the second address included in display information  
A controller which exists between a client apparatus and an image processing apparatus and which controls access from the client apparatus such that the client apparatus can use a network server...
7395380 Selective snooping by snoop masters to locate updated data  
A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less...
7386635 Electronic device circuit having a sensor function for expandably connecting a plurlity of electronic devices  
An electronic device ( 120 ) includes: an input connector ( 121 ), including at least three address pins and plural data pins; a function chip ( 123 ), including address pins and data pins...
7386619 System and method for allocating communications to processors in a multiprocessor system  
In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a...
7376810 Integrated device with multiple reading and/or writing commands  
An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an...
7373439 System method using material exchange format (MXF) converting program for audio and video data files having routines that generates attribute data from audio and video data file  
An MXF parser thread 43 parses data MXF_D, being, mixed together, a plurality of video data PIC, a plurality of audio data SOU, and system data SYS. Then, it generates video file attribute data...
7366843 Computer system implementing synchronized broadcast using timestamps  
A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by...
7366803 Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty  
A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data...
7363440 System and method for dynamically accessing memory while under normal functional operating conditions  
A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a...
7356627 Device identification  
A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more...
7346051 Slave device, master device and stacked device  
A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of...
7343451 Disk array device and remote copying control method for disk array device  
Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional...
7328286 Automatic addressing on bus systems  
In a method and apparatus for automatic address allocation among control devices connected to a bus system in a vehicle, and address allocation period sending a message on the common data bus line....
7302509 Method and data structure for random access via a bus connection  
A method for addressing cells in devices via an I2C bus is suggested, in which the common addressing scheme is supplemented by a ‘Data Transfer Mode’ byte. The ‘Data Transfer Mode’ byte...
7295134 Terrain avoidance method and device for an aircraft  
An aircraft terrain avoidance method and device may employ a collision warning section that transmits a caution signal when the aircraft risks colliding with the terrain at the end of a first...
7287102 System and method for concatenating data  
A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start...
RE39879 Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information  
A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which...
7272671 Means of control bits protection in a logical partition environment having a first and second distinct operating system  
A method, system, and apparatus for secure programmable addressing is provided by relocating functions within a multifunctional chip to be distributed across multiple logical partitions and...
7266667 Memory access using multiple sets of address/data lines  
Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using...
7260669 Semiconductor integrated circuits  
When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus...
7254690 Pipelined semiconductor memories and systems  
The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor...
7216185 Buffering apparatus and buffering method  
Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line...
7197549 On-demand address pools  
A method for on-demand management of Internet Protocol (IP) address pools includes allocating an unused IP address from a local IP address pool designated for a remote domain if a request to...
7194613 Communication protocol for serial peripheral devices  
A computing system comprising a host device which includes a serial communication bus and a processor for controlling communication over the serial communication bus. The computing system further...
7191254 Microcomputer and evaluation device, evaluation method thereof  
A microcomputer which outputs address data to an external device for evaluating the address data comprising an address counter specifying an address of a program memory, an address data output...
7187741 Clock domain crossing FIFO  
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links...
7184524 Rules based real-time communication system  
A rules-based real-time messaging system for groups of users, in which an availability status may be maintained in association with each user. Clients are communicably coupled to a real-time...
7162258 Light fixture wireless access points  
An access point for a wireless local area data communications network is designed to derive power from a lighting fixture. In one arrangement, the access point includes a housing configured to be...
Matches 1 - 50 out of 261 1 2 3 4 5 6 >