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7603493 |
Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
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7596639 |
Skip mask table automated context generation
Skip logic is provided in a storage controller that informs a direct memory access (DMA) context list manager of consecutive ones and zeroes in a skip mask table. The DMA context list manager then...
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7587535 |
Data transfer control device including endian conversion circuit with data realignment
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
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7587529 |
Method for controlling memory in mobile communication system
Disclosed is a method for controlling a memory in a mobile communication system. The method includes receiving certain frame control information by a Data Receiver Block (DRB) from a MAP decoder,...
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7584308 |
System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel
A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device...
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7555576 |
Processing apparatus with burst read write operations
A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The...
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7543093 |
Method and system for stream burst data transfer
The method and system for data transfer between the master device and the slave device through the bus are presented. It includes arbitrating the requests of bus usage from the master device; the...
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7543088 |
Various methods and apparatuses for width and burst conversion
Methods and apparatuses are described for a communication system. The communication system comprises an initiator core supporting a first burst capability as well as a target core supporting a...
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7543087 |
Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device
A transmit offload engine (TOE) such as an intelligent network interface device (INIC), video controller or host bus adapter (HBA) that can communicate data over transport protocols such as...
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7539783 |
Systems and methods of media management, such as management of media to and from a media storage library, including removable media
A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media...
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7533322 |
Method and system for performing function-specific memory checks within a vehicle-based control system
Integrity of data stored in a memory space associated with a vehicle-based control system (such as a traction enhancement system) is verified through the use of sub-module checksums. A checksum for...
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7526593 |
Packet combiner for a packetized bus with dynamic holdoff time
Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed...
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7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
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7502873 |
Facilitating access to status and measurement data associated with input/output processing
Input/output processing is facilitated by readily enabling access to information associated with input/output processing. This information includes status information and measurement data provided...
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7500023 |
Facilitating input/output processing by using transport control words to reduce input/output communications
Input/output processing is facilitated by reducing communications between input/output communications adapters and control units during input/output processing. The number of exchanges and...
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7475168 |
Various methods and apparatus for width and burst conversion
Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core....
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7461183 |
Method of processing a context for execution
A method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes...
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7434009 |
Apparatus and method for providing information to a cache module using fetch bursts
Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to...
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7418535 |
Bus system and method of arbitrating the same
A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB),...
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7409471 |
Data transfer control device for data transfer over a bus, electronic equipment and method for data transfer over a bus
When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also...
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7404017 |
Method for managing data flow through a processing system
A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write...
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7398335 |
Method and system for DMA optimization in host bus adapters
Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read...
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7392329 |
System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices
In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The...
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7380027 |
DMA controller and DMA transfer method
A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control...
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7376777 |
Performing an N-bit write access to an M×N-bit-only peripheral
A system-on-chip ( 100 ) includes a 16-bit DSP ( 102 ), a 16-bit data bus ( 202 ) coupled to the DSP, at least one 32-bit-only peripheral ( 110 ), a 32-bit data bus ( 212 ) coupled to the...
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7376763 |
Method for transferring data from a memory subsystem to a network adapter by extending data lengths to improve the memory subsystem and PCI bus efficiency
A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the...
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RE40261 |
Apparatus and method of partially transferring data through bus and bus master control device
A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data...
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7334081 |
System and method for optimizing sequential XOR command performance
An RPO algorithm in a HDD coalesces LBA-sequential XOR commands in pipes, and passes the pipes to a lower level execution engine. The execution engine executes XOR reads and write separately to...
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7334061 |
Burst-capable interface buses for device-to-device communications
Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device....
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7334060 |
System and method for increasing the speed of serially inputting data into a JTAG-compliant device
A JTAG-compliant device is configured to receive data through the control (TMS) line in addition to being configured to receive data through the input (TDI) line. A burst-write instruction is made...
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7334059 |
Multiple burst protocol device controller
Multiple burst memory access handling protocols may be implemented at the hardware level or evaluated and selected during design of the hardware. The appropriate burst protocol may be selectable...
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7330917 |
Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data
Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the...
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7328288 |
Relay apparatus for relaying communication from CPU to peripheral device
In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information...
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7310717 |
Data transfer control unit with selectable transfer unit size
A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data...
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7301954 |
Multiple-buffer queueing of data packets with high throughput rate
The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data...
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7290066 |
Methods and structure for improved transfer rate performance in a SAS wide port environment
Methods and associated structure for utilizing multiple ports or PHYs comprising a SAS wide port to improve transmission bandwidth utilization for a single large I/O request. In one aspect hereof,...
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7280539 |
Data driven type information processing apparatus
In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other...
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7275119 |
Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an...
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7272070 |
Memory access using multiple activated memory cell rows
For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common...
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7254658 |
Write transaction interleaving
A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write...
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7251192 |
Register read for volatile memory
Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read...
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7200690 |
Memory access system providing increased throughput rates when accessing large volumes of data by determining worse case throughput rate delays
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case...
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7191162 |
FIFO interface for flag-initiated DMA frame synchro-burst operation
The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an...
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7188197 |
Data transferring apparatus for transferring liquid ejection data and a liquid ejecting apparatus
A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for...
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7185173 |
Column address path circuit and method for memory devices having a burst access mode
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and...
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7167932 |
System and method for DMA data transferring apparatus and liquid ejection apparatus
Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is...
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7165129 |
Method and apparatus for self-tuning transaction batching
In a transaction system, a dynamic batching process enables efficient flushing of data in a data buffer to a stable storage device. The transaction system uses constant values and dynamic values...
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7162550 |
Method, system, and program for managing requests to an Input/Output device
Provided are a method, system, and program for managing requests to an Input/Output (I/O) device. The I/O requests directed to the I/O device are queued and a determination is made as to whether a...
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7155541 |
Tables with direct memory access descriptor lists for distributed direct memory access
A direct memory access (DMA) descriptor table to control DMA of information in a memory is disclosed. The DMA descriptor table includes one or more DMA descriptor lists stored in the memory. Each...
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7149824 |
Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
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