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7337264 Storage control system and method which converts file level data into block level data which is stored at different destinations based on metadata of files being managed  
A first storage control system comprises a CHN connected to a LAN CN. The CHN comprises a NAS processor and I/O processor. The I/O processor judges whether all or a portion of block level data is...
7337240 Virtualization of I/O adapter resources  
A method and apparatus relates to hardware-to-hardware data transmission in computer systems, and in particular, it relates to method and system for operating I/O adapters attaching either one or...
7334058 File input/output control device and method for the same background  
A file input/output control device for dividing a file into a plurality of fragments which are distributed to a plurality of storage devices. The file input/output control device 200, upon...
7334068 Physical layer device having a SERDES pass through mode  
A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device...
7334065 Multiple data bus synchronization  
Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions...
7323974 Method and arrangement for suppressing incorrect messages in monitoring systems  
The invention relates to a method and to an arrangement for eliminating false messages in monitoring systems for electronic devices, especially for sensor circuits in motor vehicles. According to...
7325080 Data collection system  
A transfer apparatus transmits template information to each of a plurality of input/output units, wherein the template information indicates an area where an individual data relative to the...
7320040 Data distribution system  
A transfer apparatus receives, from a controller, a bit string including a plurality of individual data addressed to plural input/output units. The bit string is divided into data fragments. The...
7313636 Methods and structure for supporting persistent reservations in a multiple-path storage environment  
A persistent reservation emulation structure to emulate exclusive reservation SCSI-3 protocol features in a host system having multiple paths to a storage device. An enhanced multiple-path driver...
7310717 Data transfer control unit with selectable transfer unit size  
A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data...
7299302 Direct memory access control apparatus and method  
In a DMA control apparatus for controlling data transfer from a memory to a transfer destination apparatus in accordance with a command assigned from a processing apparatus, a data transfer command...
7299307 Analog I/O with digital signal processor array  
Embodiments of the present invention relate to a programmable logical semiconductor device which is tailored for implementing digital signal processing functions. The programmable logical...
7299303 System and method for pendant bus for serially chaining multiple portable pendant peripherals  
A communication protocol for use between serially chained portable pendant peripherals and a portable host device. The bus communications system protocol enables multiple low power input/output...
7295207 Method for managing animation chunk data and its attribute information for use in an interactive disc  
In accordance with one or more embodiments, a method of managing animation data and related control data for recording on an enhanced navigation medium is provided. The method comprises...
7293121 DMA controller utilizing flexible DMA descriptors  
A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a...
7290066 Methods and structure for improved transfer rate performance in a SAS wide port environment  
Methods and associated structure for utilizing multiple ports or PHYs comprising a SAS wide port to improve transmission bandwidth utilization for a single large I/O request. In one aspect hereof,...
7287104 Interface circuit for card-type memory, ASIC including interface circuit, and image forming apparatus including ASIC  
An interface circuit reads data for a few sectors from a card-type memory and stores the data in a buffer. When a receiving unit receives a read-access from an image forming apparatus, a data...
7281065 Long latency interface protocol  
A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control...
7277964 Data routing and processing device for flexibly performing different functionalities using multiple distinct processors  
The present invention relates to a data routing and processing device comprising a data bus, a router for managing communications on the data bus, data processing unit and a local memory for...
7275224 Method for providing an area optimized binary orthogonality checker  
A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is...
7272668 System having backplane performance capability selection logic  
A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical...
7272671 Means of control bits protection in a logical partition environment having a first and second distinct operating system  
A method, system, and apparatus for secure programmable addressing is provided by relocating functions within a multifunctional chip to be distributed across multiple logical partitions and...
7269534 Method to reduce IPMB traffic and improve performance for accessing sensor data  
An information handling system is provided with a BIOS and a baseboard management controller. The baseboard management controller is provided with non-standard functionality that enables the BIOS...
7269671 Systems, methods and computer program products for leakage-proof program partitioning  
Systems, methods and computer program products partition a whole program when it does not fit in a device's memory. Minimal, safe program partitions are downloaded from the server on demand into...
7257651 Sequential data transfer detection using addresses of data transfer requests to control the efficiency of processing the data transfer requests  
A method of detecting sequential data transfer requests, includes determining whether a first data transfer request crosses a boundary address, and, if it does, determining if the first data...
7254679 Computer system for data processing and method for the transfer of an array segment of an affine-indexed multi-dimensional array referenced in a loop nest from a first memory to a second memory  
Computer system for electronic data processing having programmable data transfer units used for transferring data from a first memory in which data is stored in a form of a multi-dimensional array...
7249204 Data transfer control device electronic equipment and method data transfer control  
A data transfer control device and electronic equipment that make it possible to implement high-speed data transfer while observing restriction that prevent the traversing of page boundaries. A...
7246179 System and method for controlling mass storage class digital imaging devices  
A method is provided for controlling a Mass Storage Class Digital Imaging Device using a SCSI pass through protocol. The protocol is based on industry standard SCSI protocol with modifications and...
7240131 Method and apparatus for improving the process of making independent data copies in a data processing system  
A PRECOPY command identifies source and destination devices. Data begins to transfer from the source device to the destination device in a background mode under the control of a copy program that...
7239956 Apparatus for processing signals from sensors incorporated in in-vehicle power train and system using the apparatus  
An apparatus is provided for processing a signal outputted by a sensor installed in a power train control system mounted in a vehicle, the signal indicating an operating state of the power train...
7237044 Information processing terminal and transfer processing apparatus  
The invention provides an apparatus wherein, when the same main data is to be transferred to a plurality of information processing terminals, passage of the same main data or descriptor on a shared...
7234005 System and method of setting parameters of peripheral device when an operation ratio of a command exceeds predetermined value  
A method of setting a parameter of a peripheral device, for controlling an operation of the peripheral device includes collecting and storing a command issued for the peripheral device by an...
7234007 Adjustable elasticity FIFO buffer have a number of storage cells equal to a frequency offset times a number of data units in a data stream  
A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method...
7234004 Method, apparatus and program product for low latency I/O adapter queuing in a computer system  
In a computer system, an I/O adapter comprises at least one I/O request mailbox for receiving I/O requests and data from a CPU. The mailbox is connected to at least one I/O request queue storage...
7228401 Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor  
The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to...
7225279 Data distributor in a computation unit forwarding network data to select components in respective communication method type  
A data distributor in a computational unit of an integrated circuit is enclosed. The data distributor receives data from a network and distributes the data to a plurality of components within the...
7225278 Method and apparatus for controlling direct access to memory circuitry  
Method and apparatus for controlling direct access to memory circuitry by a device is described. In one example, a streaming interface is configured to transmit and receive a communication sequence...
7222198 System for transferring data between devices by making brief connection with external contacts that extend outwardly from device exterior  
Disclosed are systems and methods for transferring data. In one embodiment, a system and method pertain to configuring a first device to send data, touching an external contact of the first device...
7216182 Shared storage arbitration  
The invention provides an arbitration unit adapted for controlling accesses to a shared storage. The arbitration unit comprises a set of interfaces adapted for connecting a plurality of units with...
7213084 System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit  
In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more...
7206233 Memory system with parallel data transfer between host, buffer and flash memory  
A memory system is provided which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and...
7206872 System and method for insertion of markers into a data stream  
A system and method are provided for inserting Interval Markers in a data stream comprising data blocks. Included is a Buffer having a predetermined number of registers for temporarily and storing...
7206866 Continuous media priority aware storage scheduler  
The present invention relates to a system and methodology to facilitate I/O access to a computer storage medium in a predictable and efficient manner. A scheduling system is provided that mitigates...
7203771 Apparatus, method and computer-readable medium for supplying a signal based on a user input to either a touch pad or an optical device  
A portable computer provided with a power switch, a drive for an optical device, an audio signal processing unit processing the audio data of a disk inserted into the optical device drive, and an...
7200451 Method for consistent on/off object to control radios and other interfaces  
In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware...
7200691 System and method for efficient DMA transfer and buffering of captured data events from a nondeterministic data bus  
A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system...
7200690 Memory access system providing increased throughput rates when accessing large volumes of data by determining worse case throughput rate delays  
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case...
7196805 Consumer level device for automatically transferring digital images to an internet-based service provider  
An apparatus and method are provided for processing digital imagery. A reference platform device is provided with network and telephone connectivity that enable it to establish a connection with a...
7191259 Method and apparatus for fast integer within-range compare  
A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data...
7191162 FIFO interface for flag-initiated DMA frame synchro-burst operation  
The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an...