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6438627 |
Lower address line prediction and substitution
An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst...
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6434643 |
Transmission of status information by a selected one of multiple transfer modes based on the cause for sending the status information
A peripheral device and peripheral device control method assure the immediacy of status information while opening the greatest possible bandwidth when communicating status information using a USB...
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6433883 |
Image processing apparatus
The present invention is to provide an image processing apparatus which comprises connection means for connecting to a computer network to which a plurality of computers are connected and record...
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6434636 |
Method and apparatus for performing high bandwidth low latency programmed I/O writes by passing tokens
A method and apparatus performs high bandwidth low latency programmed I/O (PIO) write operations by passing tokens. A computer system in accordance with the present invention includes a plurality...
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6434692 |
High-throughput interface between a system memory controller and a peripheral device
A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures....
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6427178 |
Software modem having a multi-task plug-in architecture
A multi-task structure for a software modem including a plurality of self-contained executable entities. The executable entities include at least a controller and a data pump with the controller...
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6425023 |
Method and system for gathering and buffering sequential data for a transaction comprising multiple data access requests
Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read...
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6425047 |
Process containing address decoders suited to improvements in clock speed
A processor that accesses a plurality of regions allocated to memory includes: a judging unit for judging which region is accessed based on an access address; an assuming unit for assuming which...
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6421683 |
Method and product for performing data transfer in a computer system
Disclosed is a system for performing online data queries. The system for performing online data queries is a distributed computer system with a plurality of server nodes each fully redundant and...
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6421744 |
Direct memory access controller and method therefor
Direct memory access controller (DMAC) ( 54 ) adapted to directly execute C language style FOR tasks assigned by a processor ( 70 ), where the FOR task includes a movement of a data element from a...
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6421742 |
Method and apparatus for emulating an input/output unit when transferring data over a network
In an example embodiment, a method of transferring data to or from an input/output unit across a network emulates a message passing protocol. A message sent from a host device to the input/output...
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6412030 |
System and method to optimize read performance while accepting write data in a PCI bus architecture
The present invention is a system and method that minimizes discarding of a pending read transaction in a peripheral component interconnect (PCI) bus architecture due to an arrival of a write...
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6405267 |
Command reordering for out of order bus transfer
A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory...
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6405268 |
Dynamic block processing in a host signal processing modem
A host signal processing (HSP) modem or transceiver includes a transmit buffer and a receive buffer. The transmit buffer stores multiple blocks of information representing a transmit signal, and...
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6401144 |
Method and apparatus for managing data transfers between peripheral devices by encoding a start code in a line of data to initiate the data transfers
A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the...
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6397270 |
System for indirect communication between two computers, each having write access to its own portion of a dual-access disk drive and read access to the entire drive
A system for secure data transfer using a dual-access disk drive. The disk drive is connected to a first computer and a second computer. The first computer may be connected to a first network and...
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6397269 |
Multiplexing pins of a PC card for providing audio communication between the PC card and host computer
A method and apparatus multiplexes pins of a PC card ( 104 ) to provide communication of two-way, high quality audio data between the PC card and a host computer ( 102 ) over a conventional PC card...
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6385671 |
Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field
The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and...
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6378007 |
Data encoding scheme
In a tape drive, or other storage device, used for storing computer data, both record data and record structure information such as file marks are encoded with codewords to form an encoded data...
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6377650 |
Counter register monitor and update circuit for dual-clock system
An improved counter register ( 30 ) and method of transferring data from a host data bus ( 29 ) controlled by a first clock source (BCLK) to the cycle timer ( 18 ) controlled by a second clock...
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6370602 |
Control B protocol for Postscript™ devices
A Control B protocol for PostScript™ devices allows data to be compressed and transmitted to the PostScript™ device without the need of having bi-directional communications between the sending...
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6370605 |
Switch based scalable performance storage architecture
Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system...
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6366977 |
Semiconductor storage device employing cluster unit data transfer scheme and data management method thereof
A semiconductor storage device for reducing data transmission overhead and thereby reducing a drop in the data transmission rate is provided, together with a data management method therefor. A...
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6360287 |
Method and apparatus for asynchronous communication over a standard data bus using a plurality of data descriptors having still image data written therein
Data having a small amount of data, such as still image data, is transmitted by using asynchronous packets. A source apparatus writes data which can be selected from a data source block into a data...
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6356962 |
Network device and method of controlling flow of data arranged in frames in a data-based network
A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in...
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6356961 |
Method and apparatus for minimizing an amount of data communicated between devices and necessary to modify stored electronic documents
In a wireless and/or wireline communications system ( 100 ), a method ( 400-536 ) and apparatus ( 200 ) for minimizing an amount of data ( 300 ) communicated between a source device ( 107, 108, 112...
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6349354 |
Method to reduce system bus load due to USB bandwidth reclamation
A method and system for reducing system bus load due to bandwidth reclamation on a Universal Serial Bus. A device residing on a USB may not be able to accept or provide data at the maximum rate...
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6347345 |
Information transfer apparatus having control unit with BTL transceiver applying transmission enable signal inputted from ethernet processor module through backplane to control unit
The present invention relates to an ATM-LAN(Asynchronous Transfer Mode-Local Area Network) switch, and in particular to an information transferring apparatus between processors of the ATM-LAN which...
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6341317 |
Method and apparatus for managing a log of information in a computer system including an intelligent storage system
A method and apparatus for managing a log of information in a computer system including a host computer and a storage system that stores data accessed by the host computer. The computer system...
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6339802 |
Computer program device and an apparatus for processing of data requests using a queued direct input-output device
A computer program device and an apparatus for proper processing of data requests. The apparatus determines which device is able to handle data requests in a computing network environment...
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6339800 |
Method for transmitting data between a microprocessor and an external memory module by using combined serial/parallel process
A method for transmitting data between a microprocessor and an external memory module through external package pins of the microprocessor, which includes the steps of: a) deciding N-bit full sized...
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6338131 |
Network system with TCP/IP ACK reduction
A system in which a personal computer sends messages into a TCP/IP network using a conventional dial-up link and downloads data from the TCP/IP network using a high-speed one-way satellite link. A...
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6338103 |
System for high-speed data transfer using a sequence of overlapped global pointer signals for generating corresponding sequence of non-overlapped local pointer signals
A circuit architecture and methodology for providing burst data transfer in high-speed digital circuit applications implements a sequence of overlapped global-pointer signals for generating...
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6338102 |
Efficient data transfer mechanism for input/output devices having a device driver generating a descriptor queue and monitoring a status queue
A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and...
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6336150 |
Apparatus and method for enhancing data transfer rates using transfer control blocks
The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for...
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6334161 |
System for reverse data transmission flow control wherein command is transferred by asynchronous transfer mode while data is transferred by isochronous transfer mode
A host computer logs in an image providing device such as a scanner connected by a serial bus, and reverses flow control of data transfer by issuing a Reverse command. The image providing device...
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6332171 |
Self-contained queues with associated control information for receipt and transfer of incoming and outgoing data using a queued direct input-output device
A queuing method and apparatus for receipt and transfer of incoming and outgoing data inn a network environment having a main storage. The mechanism includes at least one set of dedicated input...
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6330631 |
Data alignment between buses
A bus bridge for a computer system for bridging first and second buses includes a shift and accumulate unit. The shift and accumulate unit includes a shifter having an input connected to receive...
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6330623 |
System and method for maximizing DMA transfers of arbitrarily aligned data
A direct memory access engine (DMA) system and method for maximizing DMA transfers of arbitrarily aligned data. The present invention utilizes physical region descriptors (PRD) stored in memory to...
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6327205 |
Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate
A system enables the capture of incoming signals from different components when the skew between the different components is higher than the signal rate. The system comprises a first port for...
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6324600 |
System for controlling movement of data in virtual environment using queued direct input/output device and utilizing finite state machine in main memory with two disjoint sets of states representing host and adapter states
A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing...
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6321310 |
Memory architecture for a computer system
A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for...
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6314474 |
Efficient information exchange between an electronic book and a cartridge
The present invention is a method and apparatus for exchanging information between an electronic book and a cartridge. The electronic book has an on-board storage and the cartridge contains a...
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6311237 |
System including single host buffer for transmit and receive data and reception buffer in interface device having stand-by area for use by host buffer when abnormal state is detected
In the event that a host device does not have a transmitting FIFO and receiving FIFO independently, but shares one FIFO for both transmission and reception, and an error occurs at the destination...
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6311235 |
UART support for address bit on seven bit frames
An asynchronous serial port provides increased serial throughput. In data frames comprising eight data bits, at least one bit may be disabled. The status and communication bits within the frame are...
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6311294 |
Device and method for efficient bulk data retrieval using a universal serial bus
A USB device for communicating data from the device to a USB host is provided. The USB device may have an interrupt or isochronous endpoint for communicating interrupts to the host and a bulk data...
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6298398 |
Method to provide checking on data transferred through fibre channel adapter cards
The present invention provides checking on information units sent and received as packets over fiber channel networks by providing check bits on the header information and separate check bits on...
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6298437 |
Method for vectoring pread/pwrite system calls
A method is provided for I/O data transfer between memory and disk. In one embodiment, an application program generates N data transfer requests. Thereafter, a data transfer list is created that...
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6292855 |
Method to allow hardware configurable data structures
A set of registers are provided for a protocol engine driving I/O transactions requested by a host. A fixed set of defined data elements are determined for the protocol under which the I/O...
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6292888 |
Register transfer unit for electronic processor
A processing system has an instruction processor (IP), register files for storing data to be processed by the IP, such as a thread context, and a register transfer unit (RTU) connected to the...
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