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7620764 |
System, apparatus and method for data path routing configurable to perform dynamic bit permutations
A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex...
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7620741 |
Proxy-based device sharing
A method is provided for supporting device sharing between hosts via a bus fabric. A master host owns a device tree and provides IO services to at least one client host. The client host comprises...
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7613961 |
CPU register diagnostic testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of...
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7603509 |
Crossbar switch with grouped inputs and outputs
A crossbar switch is optimized for area, performance, and power by grouping the data lines that comprise the input ports and output ports of the switch into a plurality of separate cross-point...
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7603508 |
Scalable distributed memory and I/O multiprocessor systems and associated methods
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one...
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7603478 |
Displaying routing information for a measurement system
Computer-implemented system and method for presenting routing information in a measurement system. A meta-routing tool receives user input specifying a device, then retrieves a topography...
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7596653 |
Technique for broadcasting messages on a point-to-point interconnect
A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a...
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7594061 |
Motherboard with multiple graphics interfaces
A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the...
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7594060 |
Data buffer allocation in a non-blocking data services platform using input/output switching fabric
Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement...
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7590791 |
Optimized switching method
There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a...
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7587545 |
Shared memory device
A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory...
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7587543 |
Apparatus, method and computer program product for dynamic arbitration control
A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current...
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7584320 |
Sliced crossbar architecture with no inter-slice communication
A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS...
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7584319 |
Connection management in serial attached SCSI (SAS) expanders
A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to...
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7581055 |
Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and...
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7568064 |
Packet-oriented communication in reconfigurable circuit(s)
A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.
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7568063 |
System and method for a distributed crossbar network using a plurality of crossbars
A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a...
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7565475 |
Layered crossbar for interconnection of multiple processors and shared memories
Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path...
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7552262 |
Integration of an operative standalone router into a multi-chassis router
A standalone router is integrated into a multi-chassis router. Integrating the standalone router into a multi-chassis router requires replacing switch cards in the standalone router with...
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7546408 |
Method and apparatus for communication within a programmable device using serial transceivers
Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module....
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7546399 |
Store and forward device utilizing cache to store status information for active queues
In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a status storage device to track...
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7533211 |
Cross-bar switching in an emulation environment
A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically...
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7526595 |
Data path master/slave data processing device apparatus and method
An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data...
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7523239 |
Bus communication system
A bus communication system is equipped with an operation scheme based on a trouble detection method that prevents a halt of the entire bus communication system by partially operating the system...
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7519761 |
Transparent PCI-based multi-host switch
A transparent PCI-based multi-host switch. A switch is configured with multiple north facing ports to couple the switch to multiple hosts. The multi-host switch can be included in a variety of...
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7512729 |
Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency
A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes...
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7509141 |
Software defined radio computing architecture
An improved architectural approach for implementation of a low power, scalable topology for a software defined radio (SDR). Low power processors and switching elements forming building blocks are...
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7490189 |
Multi-chip switch based on proximity communication
A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor...
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7472217 |
Asynchronous/synchronous KVMP switch for console and peripheral devices capable of switching KVM channels and peripheral channels to common or different computers
A signal switch for sharing a video monitor, a plurality of console devices compliant with an industry standard and one or more than one peripheral device in any of a plurality of computer systems,...
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7459933 |
Programmable crossbar signal processor used in image processing
A method including storing two-dimensional binary data in the form of high or low resistance states into a crossbar array with a programmable material layer and transforming the two-dimensional...
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7451260 |
Interleave mechanism for a computing environment
Provided is a system to communicate data in a computing environment, comprising an interleaving mechanism operable to interleave data being communicated across the computing environment according...
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7447828 |
Programmable crossbar signal processor used as morphware
A method includes providing a crossbar array including a programmable material layer, wherein the crossbar array is configured to function as part of a signal processing system and reprogramming at...
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7426709 |
Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system
An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to...
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7426602 |
Switch for bus optimization
There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a...
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7426601 |
Segmented interconnect for connecting multiple agents in a system
In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises...
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7426600 |
Bus switch circuit and bus switch system
A bus switch circuit having plural master side interface circuits inputting/outputting signals for plural bus masters respectively, and one or plural slave side interface circuit(s)...
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7412557 |
Apparatus and method for preventing loops in a computer network
A network device is configured in a manner to prevent connectivity loops such as one way connectivity loops. A user configures a port of the network device to have an associated state. The state...
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7412551 |
Methods and apparatus for supporting programmable burst management schemes on pipelined buses
Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters,...
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7406086 |
Multiprocessor node controller circuit and method
Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being...
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7392329 |
System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices
In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The...
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7386649 |
Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and...
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7385982 |
Systems and methods for providing quality of service (QoS) in an environment that does not normally support QoS features
Systems and methods for providing fractional bandwidth communication channels in classes of service that do not normally support these types of channels. In one embodiment, a method comprises...
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7380018 |
Peripheral bus transaction routing using primary and node ID routing information
A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing devices, a primary routing resources...
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7376799 |
System for reducing the latency of exclusive read requests in a symmetric multi-processing system
A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with...
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7373450 |
Multi-layer bus system having a bus control circuit
A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and...
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7370135 |
Band configuration agent for link based computing system
A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the...
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7363417 |
Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a...
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7363400 |
Data transfer switch
When the capacity availability of buffer memory provided to an output port of a frame to be transferred is exceeding a predetermined value, a crossbar switch is used for path change of the frame....
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7353317 |
Method and apparatus for implementing heterogeneous interconnects
Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the...
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7343442 |
Scalable distributed memory and I/O multiprocessor systems and associated methods
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one...
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