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7392329 System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices  
In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The...
7386649 Multiple processor system and method including multiple memory hub modules  
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and...
7385982 Systems and methods for providing quality of service (QoS) in an environment that does not normally support QoS features  
Systems and methods for providing fractional bandwidth communication channels in classes of service that do not normally support these types of channels. In one embodiment, a method comprises...
7380018 Peripheral bus transaction routing using primary and node ID routing information  
A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing devices, a primary routing resources...
7376799 System for reducing the latency of exclusive read requests in a symmetric multi-processing system  
A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with...
7373450 Multi-layer bus system having a bus control circuit  
A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and...
7370135 Band configuration agent for link based computing system  
A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the...
7363417 Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host  
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a...
7363400 Data transfer switch  
When the capacity availability of buffer memory provided to an output port of a frame to be transferred is exceeding a predetermined value, a crossbar switch is used for path change of the frame....
7353321 Integrated-circuit implementation of a storage-shelf router and a path controller card for combined use in high-availability mass-storage-device shelves that may be incorporated within disk arrays  
An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks...
7353317 Method and apparatus for implementing heterogeneous interconnects  
Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the...
7343442 Scalable distributed memory and I/O multiprocessor systems and associated methods  
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one...
7342413 Programmable crossbar signal processor with input/output tip interconnection  
A device including a nanowire crossbar array including a programmable material layer, at least one of input or output circuitry, and at least one array of input or output tips to provide an...
7340556 Signal switch for console and peripheral devices  
A signal switch for sharing a video monitor, a plurality of console devices compliant with an industry standard and one or more than one peripheral device in any of a plurality of computer systems,...
7340167 Fibre channel transparent switch for mixed switch fabrics  
A method and a Fibre Channel switch element are provided that allows communication between a host system and a target device attached to a proprietary switch fabric in a network. The Fibre Channel...
7330919 Television with integrated asynchronous/synchronous KVMP signal switch for console and peripheral devices  
A television with integrated signal switch ( 100 ) for sharing a television screen ( 14 ), a plurality of console devices compliant with an industry standard ( 16, 18 ) and at least one peripheral...
7305512 Programme-controlled unit with crossbar employing a diagnostic port  
A programme-controlled unit comprises a crossbar with a multiplicity of ports, a multiplicity of devices which are connected to the ports of the crossbar and can exchange data via the crossbar, and...
7302513 Programmable crossbar signal processor  
A signal processing system is taught to be formed by combining a crossbar array with programming circuitry and signal input circuitry so as to provide a linear transformation from a set of input...
7302282 Communications system for implementation of synchronous, multichannel, galvanically isolated instrumentation devices  
An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection...
7280350 Computing devices  
Each of a cluster of computing balls ( 1 ) contains within its housing ( 3 ) a photosensitive device ( 51 ) for receiving light from a light source ( 5 ) and converting it into energy to power a...
7277976 Multilayer system and clock control method  
The multilayer system of this invention is characterized by the process when a first master such as a CPU to which a clock signal is constantly supplied from a clock generator activates a second...
7275126 Sliced crossbar architecture with no inter-slice communication  
A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS...
7274690 Age selection switching scheme for data traffic in a crossbar switch  
A content addressable merged queue (camQ) architecture for high-speed switch fabrics reduces the memory requirement for crossbar switch input and output queues using memory cells and age tag...
7266632 Programmable logic device including programmable interface core and central processing unit  
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user....
7260613 Storage system, disk control cluster including channel interface units, disk interface units, local shared memory units, and connection portions, and a method of increasing of disk control cluster  
In a storage system in which: LSW 110 is a local switch, GSW 115 is a global switch, and 21 is a global shared memory unit; when a host computer 3 makes a data read request to a disk...
7249214 Sliced crossbar architecture with no inter-slice communication  
A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first...
7249207 Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domains  
An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus...
7243182 Configurable high-speed serial links between components of a network device  
A system for selectively forming high-speed serial connections between various components of a network device that includes a multiplexing switch coupled a GE slot and to the high speed serial...
7239669 Asynchronous system-on-a-chip interconnect  
Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a...
7237055 System, apparatus and method for data path routing configurable to perform dynamic bit permutations  
A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex...
7234018 Layered crossbar for interconnection of multiple processors and shared memories  
A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor...
7234011 Advanced microcontroller bus architecture (AMBA) system with reduced power consumption and method of driving AMBA system  
In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by...
7228375 System and method for efficient input/output of a computer system  
A system and method allows input/output to and from a computer system via the memory bus of a computer system. Input is accepted directly into shared memory or other memory and assigned to a...
7216195 Architecture for managing disk drives  
Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures...
7213097 Electronic control unit and electronic driving unit  
An input processing circuit is interposed between input terminals and input ports of an MPU. An output processing circuit is interposed between output ports of the MPU and output terminals. The...
7209996 Multi-core multi-thread processor  
In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another...
7206889 Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes  
A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary...
7203789 Architecture and methods for computing with reconfigurable resistor crossbars  
An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale...
7200699 Scalable, two-stage round robin arbiter with re-circulation and bounded latency  
A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a...
7197592 Method for exchanging data between several stations  
In a method for exchanging data between several stations belonging to various data bus systems. The data bus systems are spatially and physically separate from each other. The stations exchange...
7191277 Dynamic allocation of devices to host controllers  
The present technique is associated with a device-controller configuration system for a computer system having a plurality of controllers. The technique utilizes an automatic switching assembly so...
7188209 Apparatus and method for sharing I/O endpoints within a load store fabric by encapsulation of domain information in transaction layer packets  
An apparatus having a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a...
7185121 Method of accessing memory via multiple slave ports  
A crossbar switch ( 12 ) arbitrates for access from multiple bus masters ( 14, 16, 18, 20 and 22 ) to multiple addressed slave ports ( 3 and 4 ) that have overlapping address ranges. In one...
7181556 Transaction request servicing mechanism  
A data processing apparatus comprises a master device 150, 160, 170, 180 , a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to...
7174413 Switching apparatus and method for providing shared I/O within a load-store fabric  
A method enabling I/O devices to be shared among multiple operating system domains, including first communicating with each of the operating system domains according to a protocol that provides...
7174412 Method and device for adjusting lane ordering of peripheral component interconnect express  
A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral...
7174411 Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host  
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit...
7173906 Flexible crossbar switching fabric  
A crossbar switching fabric comprising a plurality of crossbar input ports and a plurality of crossbar output ports. The traffic from at least one source is directed to more than one of the...
7171542 Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins  
A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are...
7171504 Transmission unit  
A transmission unit that improves communication quality by making effective use of a line to a blocked port in compliance with a spanning tree protocol. Bridges have bridge ports and communicate at...
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