|
Match
|
Document |
Document Title |
|
|
7624221 |
Control device for data stream optimizations in a link interface
Optimization logic that optimizes a stream of requests being transmitted onto a link by a link interface unit can be enabled or disabled based on a performance metric that represents a measure of...
|
|
|
7617343 |
Scalable bus structure
A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a...
|
|
|
7613859 |
Back-off timing mechanism in a digital signal processor
Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having...
|
|
|
7610061 |
Communication device and method having a common platform
A communication device and method is provided, comprising: a signal modulator/demodulator having a digital signal processor for effecting radio communications; and an application processor (AP)...
|
|
|
7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
|
|
|
7603511 |
Cyclic buffer mechanism for receiving wireless data under varying data traffic conditions
A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile...
|
|
|
7603508 |
Scalable distributed memory and I/O multiprocessor systems and associated methods
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one...
|
|
|
7603487 |
Hardware configurable hub interface unit
A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a...
|
|
|
7594057 |
Method and system for processing DMA requests
Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system,...
|
|
|
7594047 |
Buffer circuit
Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out...
|
|
|
7590789 |
Optimizing clock crossing and data path latency
In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct...
|
|
|
7590764 |
System and method for dynamic buffer allocation
A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor...
|
|
|
7574539 |
Dynamic A-MSDU enabling
A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus...
|
|
|
7571271 |
Lane merging
A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers...
|
|
|
7570534 |
Enqueue event first-in, first-out buffer (FIFO)
In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write...
|
|
|
7568118 |
Deterministic operation of an input/output interface
In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
|
|
|
7562165 |
USB host system, AV data reproduction apparatus and AV data recording apparatus
A USB host system includes a USB host controller including a transfer memory for USB data transfer. In the transfer memory, a plurality of transfer descriptor regions are allocated. Transfer...
|
|
|
7558901 |
Apparatus and method for connecting processor to bus
An apparatus and method for connecting a processor to buses. The apparatus includes a multiplexer which, when addressing information indicating the address of a first memory connected to a...
|
|
|
7558895 |
Interconnect logic for a data processing apparatus
An interconnect logic and method are provided for controlling transaction reordering by slave logic units coupled to the interconnect logic. The interconnect logic couples master logic units and...
|
|
|
7551626 |
Queueing system for processors in packet routing operations
In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for...
|
|
|
7539810 |
System, method and storage medium for a multi-mode memory buffer device
A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a...
|
|
|
7539791 |
Method and apparatus for optimizing data buffering
A method for storing data in a first buffer and a second buffer is disclosed. The method includes: sequentially storing an incoming data into the first buffer and the second buffer according to a...
|
|
|
7536495 |
Certified memory-to-memory data transfer between active-active raid controllers
A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a...
|
|
|
7536494 |
Expandable slave device system with buffered subsystems
A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices...
|
|
|
7533216 |
Device and method for simulating a hard disk
A device and a method for simulating a hard disk are disclosed. The device has a core logic chip, a main memory module and a setting module. The setting module is used to set the main memory module...
|
|
|
7529876 |
Tag allocation method
Embodiments of the present invention provide methods and systems for allocating multiple tags to multiple requesters in back to back clock cycles. A tag pool may be divided into a predetermined...
|
|
|
7529867 |
Adaptive, scalable I/O request handling architecture in virtualized computer systems and networks
A system and method for processing input/output (I/O) requests in a virtualized computer system. I/O requests are received from a virtual machine. A set of virtual I/O channels that may be...
|
|
|
7526594 |
USB data transfer method
A method of Universal Serial Bus (USB) data transfer is provided. In one embodiment, a USB device supports a bulk-only transmission mode to transfer data with a USB host, and the USB device...
|
|
|
7526593 |
Packet combiner for a packetized bus with dynamic holdoff time
Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed...
|
|
|
7519759 |
Pipeline synchronisation device
Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging...
|
|
|
7516262 |
Data transfer apparatus with control of buses to enable reading of predetermined data sizes
A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus...
|
|
|
7514289 |
Methods and structures for facilitating proximity communication
One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a...
|
|
|
7500045 |
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system...
|
|
|
7500044 |
Digital phase relationship lock loop
In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input...
|
|
|
7496707 |
Dynamically scalable queues for performance driven PCI express memory traffic
A method, data processing system, and PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or...
|
|
|
7496698 |
System and method for efficient implementation of a shared receive queue
A method, computer program product, and a data processing system for posting and retrieving WQEs to a shared receive queue in a manner that alleviates head-of-line blocking issues is provided. The...
|
|
|
7493446 |
System and method for completing full updates to entire cache lines stores with address-only bus operations
A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor...
|
|
|
7487284 |
Transaction flow and ordering for a packet processing engine, located within an input-output hub
An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing...
|
|
|
7484031 |
Bus connection device
A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected...
|
|
|
7484030 |
Storage controller and methods for using the same
In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2)...
|
|
|
7484029 |
Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters
A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data...
|
|
|
7484028 |
Burst-capable bus bridges for coupling devices to interface buses
Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device....
|
|
|
7478189 |
Deadlock avoidance in a bus fabric
Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a...
|
|
|
7454551 |
Reconstructing transaction order using clump tags
A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in...
|
|
|
7450678 |
Asynchronous signal input apparatus and sampling frequency conversion apparatus
In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A...
|
|
|
7447826 |
Receive buffer in a data storage system
A method according to one embodiment may include receiving data in a receive buffer, the receive buffer comprising a plurality of buffers, and sending a hold command to a transmitting node...
|
|
|
7444444 |
Message processing system and method using external storage
The invention relates to a message processing system and method using an external storage medium. Upon receiving a message, the system and method examine the status of a first internal memory. If...
|
|
|
7441065 |
Method and apparatus for a two-wire serial command bus interface
A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into...
|
|
|
7424567 |
Method, system, and apparatus for a dynamic retry buffer that holds a packet for transmission
An interconnect apparatus provides for the buffering of information among a plurality of retry buffers in an output port. An additional buffer is dynamically assignable to one of the N retry buffer...
|
|
|
7424566 |
Method, system, and apparatus for dynamic buffer space allocation
An interconnect apparatus provides for the buffering of information in respective transaction buffers according to transaction type. An additional buffer is dynamically assignable to one of the...
|