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9037813 Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same  
A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation...
9032131 Systems and methods for encoding control messages in an audio bitstream  
An audio system including a first audio unit and a second audio unit coupled to the first audio unit through an audio bus. A first processor is coupled to the first audio unit. The first processor...
9009378 Method and apparatus for enhancing universal serial bus applications  
A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals...
9009380 USB transaction translator with SOF timer and USB transaction translation method for periodically sending SOF packet  
A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is...
9003082 Information processing apparatus, arithmetic device, and information transferring method  
An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in...
8996772 Host communication device and method with data transfer scheduler  
A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising...
8990494 Home storage system and method with various controllers  
In general, embodiments of the present invention provide a home storage system and method of production. Specifically, in a typical embodiment, the home storage system includes a main controller...
8990460 CPU interconnect device  
The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial...
8977823 Store buffer for transactional memory  
Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a...
8977816 Cache and disk management method, and a controller using the method  
A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid...
8972689 Apparatus, method and system for using real-time performance feedback for modeling and improving access to solid state media  
A storage processor identifies latency of memory drives for different numbers of concurrent storage operations. The identified latency is used to identify debt limits for the number of concurrent...
8954635 Buffer management using freelist buffers  
A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a...
8949500 Non-blocking processor bus bridge for network processors or the like  
Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field...
8938561 Time-sharing buffer access system  
A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first...
8930638 Method and apparatus for supporting target-side security in a cache coherent system  
A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by...
8924596 System and method for dividing and synchronizing a processing task across multiple processing elements/processors in hardware  
A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more...
8924612 Apparatus and method for providing a bidirectional communications link between a master device and a slave device  
A bidirectional communications link between a master device and a slave device includes first endpoint circuitry coupled to the master device generating forward data packets, second endpoint...
8918600 Methods for controlling host memory access with memory devices and systems  
The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access...
8918559 Partitioning of a variable length scatter gather list  
Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting...
8909844 Inter-integrated circuit (I2C) multiplexer switching as a function of clock frequency  
In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer...
8902899 Input buffered switching device including bypass logic  
A method includes receiving a first packet at an input of a switching device and determining whether to insert first data associated with the first packet into a normal buffer of the input. The...
8868809 Interrupt queuing in a media controller architecture  
Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating...
8862797 Reducing delay and delay variation in a buffer in network communications  
There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory...
8862801 Handling atomic operations for a non-coherent device  
In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the...
8850250 Integration of processor and input/output hub  
Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an...
8843675 Pipelined buffer interconnect  
A method and system to transfer data from one or more data sources to one or more data sinks using a pipelined buffer interconnect fabric is described. The method comprises receiving a request for...
8838855 Wireless station and method for selecting A-MPDU transmission characteristics  
A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus...
8838870 Baseboard management controller and method for sharing serial port  
A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized,...
8838782 Network protocol processing system and network protocol processing method  
In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized...
8832346 Data packing and unpacking engine  
Systems and methods are disclosed to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus...
8819325 Interface device and system including the same  
An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device...
8819310 System-on-chip and data arbitration method thereof  
A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response...
8788765 Buffer control system and method for a memory system having outstanding read and write request buffers  
A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system...
8782318 Increasing Input Output Hubs in constrained link based multi-processor systems  
Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are...
8769179 Method for performing distributed administration  
A master defines properties for a resource. The master assigns the properties to an owner. The owner associates the properties to an administrator object, the administrator object being an...
8760123 High voltage dedicated charging port  
Circuitry in an electronic device may be attached to external device, such as a power supply, to receive a voltage at a desired voltage level from the external device. The circuitry may assert one...
8745301 High voltage dedicated charging port  
Circuitry in a portable device may be attached to external device, such as a power supply, to receive a voltage at a desired voltage level from the external device. The circuitry may assert one of...
8745300 Auxiliary device for camera module test  
An auxiliary device includes a first interface of a bandwidth higher than about 1 Gbps for connecting a camera module, a second interface of a bandwidth higher than about 1 Gbps for connecting an...
8738833 Collaborative bus arbitration multiplex architecture and method of arbitration of data access based on the architecture  
A collaborative bus arbitration multiplex architecture includes of a main memory, a bus, a plurality of BMPDs, and a BAM. Arbitration can be done according to the following steps of awaiting...
8732378 Bus bandwidth monitoring device and bus bandwidth monitoring method  
A bus bandwidth monitoring device may include a buffer unit that is connected to a common bus, the buffer unit storing data that has been input via the common bus, a processing unit that performs...
8732374 Subscriber node of a communication system having a functionally separate transmission event memory  
A subscriber node of a communication system, a communication system and a method for transmitting a message in the communication system. The message is transmitted from a first subscriber node of...
8713219 Switching device, switch control method, and storage system  
A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual...
8688313 Remote vehicle programming system and method  
A system and method for remotely programming a vehicle including a vehicle connector with a plurality of pins in communication with one or more vehicle sub-systems or modules, a vehicle...
8683238 Mobile system on chip (SoC) and a mobile terminal including the mobile SoC  
A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled...
8677046 Deadlock resolution in end-to-end credit protocol  
A method for deadlock resolution in end-to-end credit protocol includes receiving a data frame and determining a number of credits required to transmit the data frame. The method also includes...
8677045 Transaction reordering system and method with protocol indifference  
An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller...
8670454 Dynamic assignment of data to switch-ingress buffers  
Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host...
8667205 Deadlock resolution in end-to-end credit protocol  
A system for deadlock resolution in end-to-end credit protocol includes a plurality of source controllers configured to receive data frames on an incoming link, wherein each source controller...
8654556 Registered DIMM memory system  
A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In...
8656078 Transaction identifier expansion circuitry and method of operation of such circuitry  
Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and...