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7594058 Chipset supporting a peripheral component interconnection express (PCI-E) architecture  
The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first...
7590788 Controlling transmission on an asynchronous bus  
In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the...
7590764 System and method for dynamic buffer allocation  
A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor...
7581044 Data transmission method and system using credits, a plurality of buffers and a plurality of credit buses  
A data flow management system and method in which the application and its clients are made aware of the available credits for each type of transfer before the transfer is attempted. This enables...
7565470 Serial bus device with address assignment by master device  
The present invention offers a daisy chain serial bus system. For bus construction, the slave device has a first data transmission port to transfer serial data with its upward connected device and...
7558901 Apparatus and method for connecting processor to bus  
An apparatus and method for connecting a processor to buses. The apparatus includes a multiplexer which, when addressing information indicating the address of a first memory connected to a...
7552268 Method for improving bus utilization using predictive arbitration  
A PCI bridge device includes an arbiter that uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the type of transaction a requestor...
7543101 System of accessing data in a graphics system and method thereof  
A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output...
7539809 System and method for dynamic adjustment of an information handling systems graphics bus  
PCI Express bus utilization is monitored for one or more predetermined thresholds to adjust the width of the bus in accordance with the utilization to provide power savings with minimal impact on...
7529955 Dynamic bus parking  
Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to...
7525986 Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools  
Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input...
7523243 Multi-host USB device controller  
A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate...
7516280 Pulsed arbitration system and method  
A pulsed arbitration system has a partial-address coincidence detector with a partial-address collision flag as an output. An active global word line detector and disable pulse generator receives...
7512723 Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system  
A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second...
7500042 Access control device for bus bridge circuit and method for controlling the same  
An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an...
7464207 Device operating according to a communication protocol  
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a...
7451259 Method and apparatus for providing peer-to-peer data transfer within a computing environment  
A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of...
7447803 Method and device for reducing a dataset consisting of process data to be transmitted  
A method for reducing an amount of process data to be transferred from a field device, wherein the process data includes information concerning an operating condition of the field device, and/or...
7446775 Data processor and graphic data processing device  
An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic...
7433989 Arbitration method of a bus bridge  
A bus bridge interfaces a primary-side bus with a plurality of secondary-side buses. The primary side bus is a local bus in a system and the secondary-side buses are external buses connected to the...
7412555 Ordering rule and fairness implementation  
In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of...
7412550 Bus system with protocol conversion for arbitrating bus occupation and method thereof  
A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus...
7408950 Multiple node network and communication method within the network  
A multiple node network includes a plurality of terminal nodes. A management node manages the terminal nodes. A bus connects the respective terminal nodes and the management node to one another....
7383395 Storage device  
A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared...
7380043 Method and apparatus for arbitrating for serial bus access  
In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first...
7373448 Method, system, and program for building a queue to test a device  
Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from...
7366818 Integrated circuit comprising a plurality of processing modules and a network and method for exchanging data using same  
An integrated circuit comprising a plurality of processing modules M, S and a network N; RN arranged for providing at least one connection between a first and at least one second module M, S is...
7360008 Enforcing global ordering through a caching bridge in a multicore multiprocessor system  
The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the...
7346725 Method and apparatus for generating traffic in an electronic bridge via a local controller  
A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration...
7340552 Bus control system  
In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source...
7340551 Bridge permitting access by multiple hosts to a single ported storage drive  
A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the...
7328300 Method and system for keeping two independent busses coherent  
Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a...
7313642 Bus bridge arbitration method  
A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting...
7296109 Buffer bypass circuit for reducing latency in information transfers to a bus  
A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit...
7287110 Storage device for a multibus architecture  
A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of...
7281148 Power managed busses and arbitration  
A variable speed bus has its frequency adjusted based upon bandwidth requirements of active units coupled to a variable speed bus. As units coupled to the bus are stopped, bandwidth requirements...
7266631 Isolation of input/output adapter traffic class/virtual channel and input/output ordering domains  
Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with...
7266630 CPU contained LSI  
In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the...
7260667 Data transfer device, semiconductor integrated circuit, and microcomputer  
It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access...
7254657 Dual mode capability for system bus  
A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller...
7251703 Method of time stamping to enable device bridging over dissimilar buses  
Several local IEEE1394 buses are bridged together over a second bus type to create a global bus wherein each local bus node is able to address nodes across the global bus without the local nodes...
7251702 Network controller and method of controlling transmitting and receiving buffers of the same  
In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from...
7240142 Master electronics card with an adaptive bandwidth circuit  
The bus circuit of a master electronics card in a backplane-based communications system adaptively grants the upstream bus to the slave electronics cards by the early termination of a scheduled...
7240141 Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an I/O bus of a system-on-a-chip processor  
A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a...
7228368 Polling-based apparatus and system guaranteeing quality of service  
A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities....
7225287 Scalable DMA remapping on a computer bus  
A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus...
7216183 Method for facilitating read completion in a computer system supporting write posting operations  
A method for facilitating read completion in a computer system supporting write posting operations. A posted memory write and its associated tag both need to be buffered, where the associated tag...
7203781 Bus architecture with primary bus and secondary or slave bus wherein transfer via DMA is in single transfer phase engagement of primary bus  
A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus....
7191271 Two level multi-tier system bus  
The present invention is directed to a method and apparatus utilizing a two-level, multi-tier system bus. The multi-tier system bus of the present invention allows for the flow of information to be...
7188262 Bus arbitration in low power system  
Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power...
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