|
Match
|
Document |
Document Title |
|
|
8166339 |
Information processing apparatus, information processing method, and computer program
An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a...
|
|
|
8156260 |
Data transfer device and method for selecting instructions retained in channel unit based on determined priorities due to the number of waiting commands/instructions
A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to...
|
|
|
8108583 |
Direct memory access controller system with message-based programming
A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of...
|
|
|
8099539 |
Method and system of a shared bus architecture
A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a...
|
|
|
8095744 |
Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages
The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks;...
|
|
|
8051233 |
Method and system for addressing a plurality of ethernet controllers integrated into a single chip which utilizes a single bus interface
A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet...
|
|
|
8046513 |
Out-of-order executive bus system and operating method thereof
An operating method applied to an out-of-order executive bus system includes: according to dependency constraints, linking requests using the bus system to form dependency request links having an...
|
|
|
8041868 |
Bus relay device and bus control system including bus masters, interconnect section, and bridge section
A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to...
|
|
|
8041869 |
Method and system for bus arbitration
A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention...
|
|
|
8028144 |
Memory module with reduced access granularity
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes...
|
|
|
8010723 |
Safety controller with data lock
The present invention relates to a SPC comprising at least one data processing means for realizing a first data channel 1 and a second data channel 2, and comprising a data transmission means 3...
|
|
|
8006014 |
PCI-Express data link transmitter employing a plurality of dynamically selectable data transmission priority rules
A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A...
|
|
|
7990999 |
Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools
Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input...
|
|
|
7970961 |
Method and apparatus for distributed direct memory access for systems on chip
A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct...
|
|
|
7966440 |
Image processing controller and image forming apparatus
An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the...
|
|
|
7937447 |
Communication between computer systems over an input/output (I/O) bus
Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using...
|
|
|
7934046 |
Access table lookup for bus bridge
Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing....
|
|
|
7934043 |
Data processing apparatus for controlling access to a memory based upon detection of completion of a DMA bus cycle
A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory...
|
|
|
7917706 |
SDRAM controller
A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its...
|
|
|
7868892 |
Data processor and graphic data processing device
An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic...
|
|
|
7865645 |
Bus arbiter, bus device and system for granting successive requests by a master without rearbitration
A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction...
|
|
|
7861026 |
Signal relay device and method for accessing an external memory via the signal relay device
A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main...
|
|
|
7853737 |
Data transfer and alignment device and method for transferring data acquired from memory
A communication data processing device according to an aspect of the invention includes a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories...
|
|
|
7849245 |
Bus-based communication system
A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the com...
|
|
|
7840737 |
Data processor and semiconductor integrated circuits
This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a...
|
|
|
7818485 |
IO processor
An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an...
|
|
|
7805549 |
Transfer apparatus and method
There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first...
|
|
|
7779189 |
Method, system, and computer program product for pipeline arbitration
A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by...
|
|
|
7779187 |
Data communication circuit and arbitration method
A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to...
|
|
|
7774529 |
Bus communication apparatus that uses shared memory
Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a...
|
|
|
7765348 |
Configurable two-wire interface module
A telecommunications system and constituent two-wire interface module. The two wire interface module includes a logic component configured to communicate over the same pair of wires using different...
|
|
|
7765350 |
Method and system for bus arbitration
A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention...
|
|
|
7747809 |
Managing PCI express devices during recovery operations
A PCI Express system comprising: a PCI Express adapter; and a PCI Express root complex coupled to the PCI Express adapter, the PCI root complex including: a protocol stack coupled to the PCI...
|
|
|
7739461 |
DRAM power management in a memory controller
A memory controller uses a power- and performance-aware scheduler which reorders memory commands based on power priorities. Selected memory ranks of the memory device are then powered down based on...
|
|
|
7739425 |
Two channel computer bus architecture
Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on...
|
|
|
7724602 |
Memory controller with programmable regression model for power control
A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles...
|
|
|
7725759 |
System and method of managing clock speed in an electronic device
A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input...
|
|
|
7694051 |
Method for calculating master/slave response time-out under continuous packet format communications protocol
A method of detecting master/slave response time-out under continuous packet format communications protocol, which calculates the time required for the slave device to respond to a Modbus request...
|
|
|
7689746 |
Bus system employing an arbiter
A method for operating a bus system, in particular in a microprocessor or microcontroller, and a semiconductor device for performing the method is disclosed. In one embodiment, for optimizing the...
|
|
|
7673087 |
Arbitration for an embedded processor block core in an integrated circuit
Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to cor...
|
|
|
7664884 |
Media drive that creates a transfer unnecessary period, and power saving method thereof
Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof....
|
|
|
7657681 |
Arbitration circuit and function processing circuit provided therein
In an arbitration circuit in which a shared circuit such as a memory is used exclusively by one of a plurality of functional blocks at a time, an access reservation request is issued from one of...
|
|
|
7650451 |
Arbiter circuit
An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient...
|
|
|
7643410 |
Method and apparatus for managing a connection in a connection orientated environment
A bridge for translating a first storage protocol to a second protocol includes an affiliation manager. The affiliation manager accepts a connection from a host and establishes a connection between...
|
|
|
7631135 |
Processor access control device
A data processing device with an efficient mechanism for controlling bus priority of multiple processors. The device has a data memory that is accessible to the processors via each processor's...
|
|
|
7627708 |
Multi-host USB device
A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device...
|
|
|
7624222 |
South bridge system and method
A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected...
|
|
|
7594058 |
Chipset supporting a peripheral component interconnection express (PCI-E) architecture
The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first...
|
|
|
7590764 |
System and method for dynamic buffer allocation
A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor...
|
|
|
7590788 |
Controlling transmission on an asynchronous bus
In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the...
|