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7606961 |
Computer system and data pre-fetching method
A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a...
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7594057 |
Method and system for processing DMA requests
Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system,...
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7590790 |
Bus device
A bus device is used with a computer system. In the bus device, a bus-interfaced host performs data transmission in a first mode in response to a first command resulting from certain software...
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7577781 |
Bus system for use with information processing apparatus
A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection...
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7546392 |
Data transfer with single channel controller controlling plural transfer controllers
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer...
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7546391 |
Direct memory access channel controller with quick channels, event queue and active channel memory protection
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes...
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7536669 |
Generic DMA IP core interface for FPGA platform design
A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as...
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7519754 |
Hard disk drive cache memory and playback device
A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function...
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7500045 |
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system...
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7496673 |
SIMD-RISC microprocessor architecture
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
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7493425 |
Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization
A method, system and computer program product that allows a System Image within a multiple System Image Virtual Server to maintain isolation from the other system images while directly exposing a...
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7475182 |
System-on-a-chip mixed bus architecture
A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could...
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7469307 |
Storage system with DMA controller which controls multiplex communication protocol
A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer...
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7451250 |
Methods and apparatus for providing automatic high speed data connection in portable device
In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard drive (HDD), and a FireWire port,...
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7446775 |
Data processor and graphic data processing device
An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic...
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7444442 |
Data packing in a 32-bit DMA architecture
A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements,...
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7444435 |
Non-fenced list DMA command mechanism
A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an...
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7433977 |
DMAC to handle transfers of unknown lengths
A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent...
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7373437 |
Multi-channel DMA with shared FIFO
A direct memory access (DMA) circuit ( 200 ) includes a read port ( 202 ) and a write port ( 204 ). The DMA circuit ( 200 ) is a multithreaded initiator with “m” threads on the read port ( 202...
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7363396 |
Supercharge message exchanger
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store...
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7350015 |
Data transmission device
A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it...
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7350014 |
Connecting peer endpoints
In one embodiment, the present invention includes a method for sending a connection request from a requestor endpoint to a target endpoint based on route information stored in the requestor...
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7349999 |
Method, system, and program for managing data read operations on network controller with offloading functions
Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one...
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7340554 |
USB host controller with DMA capability
An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to...
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7340550 |
USB schedule prefetcher for low power
A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine...
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7340548 |
On-chip bus
This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip...
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7328300 |
Method and system for keeping two independent busses coherent
Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a...
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7313641 |
Inter-processor communication system for communication between processors
A system ( 15 ) comprising at least two integrated processors (P 1 and P 2 ). These two processors (P 1 and P 2 ) are operably connected via a communication channel ( 17 ) for exchanging...
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7308557 |
Method and apparatus for invalidating entries within a translation control entry (TCE) cache
A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The...
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7290069 |
Data acquisition system which monitors progress of data storage
A pattern may be written to an allocated section of host memory to track how much data has been received in the host memory from a direct memory access controller coupled to a First In, First Out...
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7272680 |
Method of transferring data between computer peripherals
An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while...
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7266620 |
System core for transferring data between an external device and memory
A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access...
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7263572 |
Bus bridge and data transfer method
In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a...
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7260668 |
Network co-processor for vehicles
A network processor exchanges data of various descriptions via a plurality of network nodes with external network devices, such as other processors, controllers, transducers, or sensors. The...
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7260667 |
Data transfer device, semiconductor integrated circuit, and microcomputer
It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access...
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7260661 |
Processing replies to request packets in an advanced switching context
An apparatus communicates with an advanced switching (AS) fabric. The apparatus includes a transmit engine that generates a request packet for transmission to the AS fabric. The transmit engine...
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7231484 |
Method and memory controller for scalable multi-channel memory access
An electrical device is connected to at least one memory accessing unit and to a memory including at least one physical memory module. The device includes at least one access channel circuit...
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7225278 |
Method and apparatus for controlling direct access to memory circuitry
Method and apparatus for controlling direct access to memory circuitry by a device is described. In one example, a streaming interface is configured to transmit and receive a communication sequence...
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7206879 |
Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured...
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7203781 |
Bus architecture with primary bus and secondary or slave bus wherein transfer via DMA is in single transfer phase engagement of primary bus
A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus....
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7200692 |
PVDM (packet voice data module) generic bus
A generic, parallel, n-bit wide data path communication bus allows a number of major slave devices (such as DSPs, Microprocessors, ASICs, FPGAs, etc) to be used with PVDMs and other devices. A...
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7197581 |
Integrated circuit, device and method for inputting/outputting images
The integrated circuit comprises, in addition to a first bus and a first DMA controller, a second bus and a second DMA controller that mutually connects the first bus and the second bus. A main...
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7185143 |
SAN/NAS integrated storage system
In a storage system directly connected to a network, if conventional interfaces and protocols are used when an I/O command issued from a file server is transmitted to the storage system, the...
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7171509 |
Method and apparatus for host messaging unit for Peripheral Component Interconnect busmaster devices
Peripheral Component Interconnect (PCI) device contains Host Messaging Unit (HMU) which is operative to off load host processor and PCI device processor from PCI bus transfer overhead. HMU is...
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7171508 |
Dual port memory with asymmetric inputs and outputs, device, system and method
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory...
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7165125 |
Buffer sharing in host controller
A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO...
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7162564 |
Configurable multi-port multi-protocol network interface to support packet processing
A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external...
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7155554 |
Methods and apparatuses for generating a single request for block transactions over a communication fabric
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block...
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7133942 |
Sequence-preserving multiprocessing system with multimode TDM buffer
A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and...
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7133940 |
Network interface device employing a DMA command queue
A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple...
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