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8447897 |
Bandwidth control for a direct memory access unit within a data processing system
A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source...
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8447908 |
Multilevel memory bus system for solid-state mass storage
The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as...
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8429324 |
Bus-protocol converting device and bus-protocol converting method
A bus-protocol converting device includes: a command detecting unit that detects a command sent from an external-memory control device, connected to a primary bus, to a primary bus interface...
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8417845 |
Method and apparatus transferring data via universal serial bus
A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly...
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8407389 |
Atomic operations with page migration in PCIe
A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment,...
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8397000 |
System core for transferring data between an external device and memory
Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this...
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8386688 |
Modular integrated circuit with common interface
A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal...
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8375156 |
Intelligent PCI-express transaction tagging
Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods...
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8359564 |
Circuit design information generating equipment, function execution system, and memory medium storing program
A design information generating equipment is provided. A control component of the design information generating equipment, when a basic function of the plurality of functions constitutes a...
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8359420 |
External memory based FIFO apparatus
An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first...
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8335883 |
Data processing device and data processing system
To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data...
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8335576 |
Methods and apparatus for bridging an audio controller
The present invention enables the transparent bridging of an audio controller over a network between a host PC and a remote user interface system by providing a host module that presents the...
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8327055 |
Translating a requester identifier to a chip identifier
In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip...
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8321636 |
Memory reallocation and sharing in electronic systems
Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and...
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8307143 |
Interface card system
There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module...
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8301820 |
Direct memory access for advanced high speed bus
A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory...
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8296479 |
System core for transferring data between an external device and memory
Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this...
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8291124 |
Semiconductor device and data processing system having a reduced number of terminals allocated for externally accessed address
There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access...
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8281059 |
Electronic device having projection functionality
An electronic device with a projection functionality includes: a universal serial bus (USB) port, a processing circuit, a storage, a storage controller and a display circuit. The USB port receives...
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8275925 |
Methods and apparatus for improved serial advanced technology attachment performance
Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA...
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8266340 |
DMA controller
The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in...
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8254199 |
Multi-channel memory and power supply-driven channel selection
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.
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8234407 |
Network use of virtual addresses without pinning or registration
A system comprising a compute node and coupled network adapter (NA) that allows the NA to directly use CPU virtual addresses without pinning pages in system memory. The NA performs memory accesses...
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8225329 |
Tail synchronized FIFO for fast user space packet access
A network device may include a line interface to receive and transmit data units, a memory including instructions associated with a user space and a kernel space that are executable by a processor,...
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8190794 |
Control function for memory based buffers
Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base address, at least one address pointer...
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8176221 |
DMA controller
A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the...
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8165617 |
Wireless communication apparatus and communication control method
A wireless communication apparatus and a communication control method wherein even if there occurs a change in communication control information due to a function change, an appropriate correction...
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8166226 |
Apparatus and related method for maintaining read caching data of south bridge with north bridge
A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically...
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8165621 |
Memory emulation in a cellular telephone
A cellular telephone using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM,...
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8122175 |
Opportunistic transmission of software state information within a link based computing system
A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the...
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8122177 |
Direct memory access technique for use with PCIe endpoints
An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a m...
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8117357 |
System core for transferring data between an external device and memory
Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this...
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8117475 |
Direct memory access controller
A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power...
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8111721 |
Multiplexing apparatus and method
A multiplexing system (10) is provided which includes a plurality of encoders (12-15) which generates elementary streams, respectively, CPU (16), multiplexer (17), instruction memory (18), and a...
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8112560 |
Controlling complex non-linear data transfers
A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data...
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8108571 |
Multithreaded DMA controller
A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a...
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8108583 |
Direct memory access controller system with message-based programming
A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of...
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8099531 |
Information processing method and computer program comprising network card wherein a plurality of processors switches use of network card related to setting of resource flag
An information processing apparatus includes a device that performs data processing; and processors, each processor including a device driver corresponding to the device. A device driver set in...
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8086765 |
Direct I/O device access by a virtual machine with memory managed using memory disaggregation
Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the...
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8079036 |
Method and system for structured DMA transactions
Disclosed is a structured model for developing DMA code and for performing DMA transactions. This model of structured DMA transactions provides a framework with default behaviors. Developers need...
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8060672 |
Event signaling between peripheral modules and a processing unit
There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral...
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8046503 |
DMA controller, system on chip comprising such a DMA controller, method of interchanging data via such a DMA controller
A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local...
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8041855 |
Dual-bus system for communicating with a processor
A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second...
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8037229 |
Combination non-volatile memory and input-output card with direct memory access
A removable electronic circuit card having both a memory module with a non-volatile mass storage memory and a separate input-output module so that data transfers may be made through the...
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8032686 |
Protocol translation in a data storage system
A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor,...
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8020056 |
Memory channel with bit lane fail-over
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory...
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8015326 |
Central processing apparatus, control method therefor and information processing system
A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality...
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8015312 |
Scheduler for transmit system interfaces
A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the...
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7995567 |
Apparatus and method for network control
A network control apparatus and network control method is provided. The network control apparatus including: a content addressable memory receiving to store a plurality of addresses which are...
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7975090 |
Method for efficient I/O controller processor interconnect coupling supporting push-pull DMA read operations
A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and...
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