Matches 101 - 150 out of 184 < 1 2 3 4 >
Match Document Document Title
6738845 Bus architecture and shared bus arbitration method for a communication device  
A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are...
6735662 Method and apparatus for improving bus efficiency given an array of frames to transmit  
A single completion status write back is generated by a controller to inform a driver of completion of a transmission of all frames of an array of frames, as opposed to generating individual write...
6718405 Hardware chain pull  
A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to...
6708246 Signal processing device with bus ownership control function  
A signal processing device includes an integrated processor, a video processing unit coding a video signal, and an interface controlling a bus ownership between the integrated processor and an...
6701405 DMA handshake protocol  
A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central...
6701387 Adaptive data fetch prediction algorithm  
A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device...
6684267 Direct memory access controller, and direct memory access control method  
The read position or write position of data is decided by the base address of a ring buffer and an offset from the base address and the offset is updated by the amount of DMA-transferred data. When...
6681346 Digital processing system including a DMA controller operating in the virtual address domain and a method for operating the same  
A digital processing system comprises a central processing unit (CPU) operating in a virtual address domain for executing both operating system software and user software to perform various...
6671760 Switching system for controlling internal apparatuses in an exchange system  
A switching system for controlling internal apparatuses provided within an exchange system includes a central controller and a switching module including a plurality of objective apparatuses, each...
6665748 Specialized PCMCIA host adapter for use with low cost microprocessors  
Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between...
6665759 Method and apparatus to implement logical partitioning of PCI I/O slots  
A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a...
6662258 Fly-by support module for a peripheral bus  
A system is provided that includes a bus master, a bus slave and a fly-by slave interface, all coupled to a peripheral bus. A peripheral device is coupled to the fly-by slave interface. The bus...
6654818 DMA access authorization for 64-bit I/O adapters on PCI bus  
A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have...
6636925 Bus interface circuit preparation apparatus and recording medium  
An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware...
6636919 Method for host protection during hot swap in a bridged, pipelined network  
In a bridged, pipelined network (FIG. 1), a network-to-host bridge ( 140 ) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space (...
6633926 DMA transfer device capable of high-speed consecutive access to pages in a memory  
A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a...
6631431 Semaphore coding method to ensure data integrity in a can microcontroller and a can microcontroller that implements this method  
A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core and hardware external to the processor core (e.g., a DMA engine) that writes message data into a...
6629000 MPEG portable sound reproducing system and a reproducing method thereof  
Disclosed is an MPEG portable sound reproducing system and a method for reproducing sound data compressed using the MPEG method. The inventive system includes power supply means for supplying...
6584512 Communication DMA device for freeing the data bus from the CPU and outputting divided data  
When the data bus is cut off from the CPU ( 1 ) and the transmission ready signal (TXRDY) is activated, the DMA control circuit ( 10 ) reads 32 bits of data at once according to the lead address...
6546019 Duplex memory control apparatus  
A duplex memory control apparatus having a first control unit containing a first memory and a second control unit containing second memory, a first control unit and a second control unit connected...
6542951 Information handling system having integrated internal scalable storage system  
An information handling system having an integrated internal scalable switching storage system is disclosed. The information handling system includes a housing, a processor disposed in the housing...
6532232 Method and system for transporting audio/video data over a serial bus  
The present invention provides methods and a system for transporting A/V data over a serial bus. A memory space is allocated for a set of buffers to store a plurality of CIPs. Each of the CIPs...
6519671 Method of network configuration, method and apparatus for information processing, and computer-readable media  
A bridge manager (bridge management equipment) is automatically determined. In a network, bridges 51 to 54 are configured by connecting portals 41 to 48 respectively connected to buses 11 ...
6502169 System and method for detection of disk storage blocks containing unique values  
A system and method for detecting block(s)of data transferred to a disk array from a host processor system, in which the block(s) have unique, identifiable values or patterns, is provided. A direct...
6477610 Reordering responses on a data bus based on size of response  
The efficiency of an overall computer communications system is greatly improved by a new method to transfer data on a data communications bus. The method allows one or more small command structures...
6467009 Configurable processor system unit  
The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
6463482 Control, of conflict between MPC transfer and DMC transfer with measurement of instruction execution time  
A data transfer control apparatus is disclosed for controlling conflict of data transfer on a data bus connected to a microprocessor through a bridge circuit. The bridge circuit includes a...
6463483 Low latency input-output interface  
A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The...
6463491 Data transfer making efficient use of time concerning bus arbitration  
A method of transferring data from a source device to a destination device via a source-control device connected to the source device and a destination-control device connected to the destination...
6463481 Direct memory access control system for a digital scanner  
The present invention generally relates to a digital scanner for scanning images. More specifically, the present invention is directed to a method and apparatus for quickly processing and storing...
6453368 Adding a dummy data or discarding a portion of data in a bus repeater buffer memory for a second data transfer to a second bus  
A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses ...
6449665 Means for reducing direct memory access  
In a method of reducing direct memory access in a machine employing a data segmenting scheme, transfer of a repetitive block of data is detected. The repetitive block of data repeats a data word of...
6442622 Digital signal processor and digital signal processing method  
A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled...
6425021 System for transferring data packets of different context utilizing single interface and concurrently processing data packets of different contexts  
A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process...
6412028 Optimizing serial USB device transfers using virtual DMA techniques to emulate a direct memory access controller in software  
A USB-based data acquisition system including virtual DMA software which increases USB data transfer rates with minimal changes to DAQ driver level software. The virtual DMA software operates to...
6401143 Loopback direct memory access control system for a digital scanner  
The present invention generally relates to a loopback direct memory access control system for a digital scanner for processing images. More specifically, the present invention is directed to a...
6385685 Memory card utilizing two wire bus  
A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory...
6374315 Interface with connection unit for loading host computer with external storage device format control information in response to connection of host computer to connection unit  
The present invention relates to a data processing device which is also used as an interface device for connecting an external storage device to a host computer to which a card form of storage...
6363444 Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory  
A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the...
6351784 System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction  
An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent...
6263390 Two-port memory to connect a microprocessor bus to multiple peripherals  
The present invention provides a two-port memory to connect a microprocessor bus to multiple peripherals. In one embodiment, an apparatus for an IO gateway subsystem of a microprocessor includes a...
6260159 Tracking memory page modification in a bridge for a multi-processor system  
A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control...
6249833 Dual bus processing apparatus wherein second control means request access of first data bus from first control means while occupying second data bus  
In an information processing apparatus equipped with a CPU, an operating rate of this CPU is increased so as to increase a throughput of this entire information processing apparatus. The...
6219724 Direct memory access controller  
The present invention relates to a direct memory access controller, specifically to a direct memory access controller which controls the direct memory access between internal modules and high speed...
6216193 Apparatus and method in a network interface for recovering from complex PCI bus termination conditions  
A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a...
6170031 Read/write state machines for transferring data to/from host interface in a digital data storage system  
In a storage system such as an ATA compatible flash disk drive, it is common to use state machines to automate the transfer of data between a buffer in the storage system and the host processor....
6141718 Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses  
A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control...
6122699 Data processing apparatus with bus intervention means for controlling interconnection of plural busses  
This invention has as its object to improve the net processing speed by appropriately assigning the DMA processing time for attaining high-speed processing using hardware, and the software...
6078742 Hardware emulation  
The invention features a method and apparatus for use with a computer system having a memory and a bus (e.g., a PCI bus). The bus is monitored for detection of a bus cycle intended for a controller...
6055584 Processor local bus posted DMA FlyBy burst transfers  
A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory...
Matches 101 - 150 out of 184 < 1 2 3 4 >