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7620763 |
Memory chip having an apportionable data bus
A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to...
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7620756 |
Method and apparatus for updating wide storage array over a narrow bus
A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch...
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7606960 |
Apparatus for adjusting a clock frequency of a variable speed bus
An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor...
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7600112 |
Method and system of supporting multi-plugging in X8 and X16 PCI express slots
A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root...
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7600069 |
Multi-interface conversion device
A multi-interface conversion device includes a USB-to-IDE interface bridging unit, an IDE-to-SATA interface bridging unit, an IDE switching unit, and a switching logic unit. The USB-to-IDE...
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7596675 |
Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device,...
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7587571 |
Evaluation unit in an integrated circuit
An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first...
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7584321 |
Memory address and datapath multiplexing
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed...
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7581041 |
Methods and apparatus for high-speed serialized data transfer over network infrastructure using a different protocol
An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE...
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7574541 |
FIFO sub-system with in-line correction
A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first...
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7555587 |
Communication apparatus, electronic appliance and communication system including a communication apparatus in communication with an electronic appliance for data communications
A communication system, a communication apparatus, and an electronic appliance are provide. The communication system, a communication apparatus and an electronic appliance can operate at a high...
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7552267 |
Automatic detection of the bit width of a data bus
A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as...
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7542324 |
FPGA equivalent input and output grid muxing on structural ASIC memory
The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The...
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7539809 |
System and method for dynamic adjustment of an information handling systems graphics bus
PCI Express bus utilization is monitored for one or more predetermined thresholds to adjust the width of the bus in accordance with the utilization to provide power savings with minimal impact on...
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7536490 |
Method for link bandwidth management
A method for link bandwidth management between two devices in communication through a bandwidth-adjustable bus in a computer system determines which of a speed negotiation priority and a width...
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7500043 |
Array of data processing elements with variable precision interconnect
Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing...
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7496742 |
Method and system of supporting multi-plugging in X8 and X16 PCI express slots
A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root...
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7490187 |
Hypertransport/SPI-4 interface supporting configurable deskewing
A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain....
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7490186 |
Memory system having an apportionable data bus and daisy chained memory chips
A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain....
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7480757 |
Method for dynamically allocating lanes to a plurality of PCI Express connectors
A method for dynamically allocating lanes to a plurality of PCI Express connectors is disclosed that may comprise identifying whether a PCI Express device is installed into each PCI Express...
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7480756 |
Electronic data processing circuit that transmits packed words via a bus
An electronic data processing circuit contains a plurality of data handling units ( 10 a-d, 16 a-b) with data outputs, at least part of the data handling units having address outputs. The data...
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7475168 |
Various methods and apparatus for width and burst conversion
Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core....
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7469311 |
Asymmetrical bus
A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface...
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7467251 |
Flash memory data storage apparatus
A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th...
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7447825 |
PCI-E automatic allocation system
A PCI-E automatic allocation system which essentially consists of a detection module and a switch module, wherein the detection module detects the states of the logic signals on the ground pins of...
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7447824 |
Dynamic lane management system and method
A dynamic lane management system comprises at least one downstream device of a computer system configured to dynamically initiate a lane width re-negotiation operation with at least one upstream...
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7441064 |
Flexible width data protocol
A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a...
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7426598 |
Method for configuring transmitter power consumption
A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and...
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7426597 |
Apparatus, system, and method for bus link width optimization of a graphics system
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a...
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7400326 |
System and method for delivering multiple data streams via multiple buses
Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the...
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7376780 |
Protocol converter to access AHB slave devices using the MDIO protocol
A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the...
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7376777 |
Performing an N-bit write access to an M×N-bit-only peripheral
A system-on-chip ( 100 ) includes a 16-bit DSP ( 102 ), a 16-bit data bus ( 202 ) coupled to the DSP, at least one 32-bit-only peripheral ( 110 ), a 32-bit data bus ( 212 ) coupled to the...
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7370132 |
Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive...
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7366864 |
Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device,...
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7366816 |
Method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths
A method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths. Each output path includes a buffer for holding respective portions of...
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7363441 |
Portable storage apparatus and method for freely changing data bus width
A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least...
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7363417 |
Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a...
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7360007 |
System including a segmentable, shared bus
A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may...
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7343451 |
Disk array device and remote copying control method for disk array device
Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional...
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7340553 |
Data processing device and method for transferring data
The data processing device according to the invention comprises a first processing unit ( 1 ) linked to a first bus ( 5 ), a second processing unit ( 2 ) linked to a second bus ( 6 ), a first bus...
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7337260 |
Bus system and information processing system including bus system
In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of...
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7337250 |
Low latency data transmission method and system
A method of transmitting data includes:
A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word...
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7334065 |
Multiple data bus synchronization
Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions...
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7334061 |
Burst-capable interface buses for device-to-device communications
Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device....
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7328299 |
Interface for compressed data transfer between host system and parallel data processing system
An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the...
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7325087 |
Using a processor to program a semiconductor memory
A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate...
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7325086 |
Method and system for multiple GPU support
Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first...
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7308514 |
Configuring a communication link interface
Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of...
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7296108 |
Apparatus and method for efficient transmission of unaligned data
An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment...
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7293125 |
Dynamic reconfiguration of PCI express links
A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the...
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