Matches 401 - 450 out of 671 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 >
Match Document Document Title
6732217 Control and supervisory signal transmission system  
A parent station output section changes a duty ratio between a period of a level other than a predetermined power-supply voltage level and a subsequent period of the power-supply voltage level...
6728808 Mechanism for optimizing transaction retries within a system utilizing a PCI bus architecture  
A mechanism for optimizing transaction retries within a system utilizing a peripheral component interconnect (PCI) bus architecture. Specifically, one embodiment of the present invention includes a...
6728821 Method and system for adjusting isochronous bandwidths on a bus  
A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to...
6728820 Method of configuring, controlling, and accessing a bridge and apparatus therefor  
In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a...
6725315 System and method to efficiently move data from one data bus to another data bus in a network switch  
The present invention relates to a system and method to efficiently move data from one data bus to another data bus in a network switch. The method includes generating a packet cycle on a first...
6721839 Method of mapping multiple address spaces into single PCI bus  
A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first...
6721833 Arbitration of control chipsets in bus transaction  
A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second...
6721840 Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory  
A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two...
6712277 Multiple interface memory card  
A memory card and a method for operating a memory card, the memory card comprising: a memory mass storage; a first data interface with a contacting interface and a high data transfer rate; a second...
6711647 Computer system having internal IEEE 1394 bus  
A computer system that includes a computer chassis containing an IEEE 1394 bus and peripheral devices. The computer system includes a CPU, a memory, and a bridge logic unit coupling the CPU to the...
6708246 Signal processing device with bus ownership control function  
A signal processing device includes an integrated processor, a video processing unit coding a video signal, and an interface controlling a bus ownership between the integrated processor and an...
6701405 DMA handshake protocol  
A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central...
6701403 Service processor access of non-volatile memory  
Non-volatile memory access, such as firmware access by a service processor, is disclosed. The service processor asserts a controller signal to select either a first non-volatile memory, or a second...
6697904 Preventing starvation of agents on a bus bridge  
A round robin bus arbitrator that prevents bus starvation caused by an inbound buffer becoming full and forcing repetitive retries by an agent. The arbitrator performs a rotating scan of the...
6697921 Signal processor providing an increased memory access rate  
The bus width of the data bus among blocks for transferring data among respective blocks such as the memory control block, the error correction block, and the host I/F block is 32-bit width, and...
6697906 Semiconductor device supporting integrated data transfer bridging between CPU memory and I/O device  
A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a...
6694380 Mapping requests from a processing unit that uses memory-mapped input-output space  
A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A...
6694397 Request queuing system for a PCI bridge  
A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue....
6684279 Method, apparatus, and computer program product for controlling data transfer  
A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data...
6684284 Control chipset, and data transaction method and signal transmission devices therefor  
A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in...
6678780 Method and apparatus for supporting multiple bus masters with the accelerated graphics protocol (AGP) bus  
A method and apparatus for supporting multiple bus masters on an AGP bus is presented. A first bus master is configured as an AGP bus master and utilizes the AGP request portion of the AGP bus...
6675251 Bridge device for connecting multiple devices to one slot  
A bridge includes a first port connected to a Primary bus, and second ports respectively connected to second buses. The first port includes a PCI master, a PCI slave and an AGP master. Each of the...
6675284 Integrated circuit with multiple processing cores  
An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication...
6675248 Apparatus, method and system for accelerated graphics port bus bridges  
A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP...
6668299 Software interface between a parallel bus and a packet network  
A bridge device, for coupling a parallel bus to a packet network, includes a bus interface adapter, coupled to the parallel bus so as to receive bus cycles from a master device on the bus. An...
6658508 Expansion module with external bus for personal digital assistant and design method therefor  
An expansion module for a Handspring Visor includes a multi-master AMBA Advanced System Bus (ASB). The Springboard bus of the visor is coupled to the ASB bus via Springboard-to-ASB-bus bridge. This...
6658519 Bus bridge with embedded input/output (I/O) and transaction tracing capabilities  
A transaction tracing circuit for use with a bus bridge that is couplable to at least a first and second bus. The transaction tracing circuit includes at least one set of trace control registers...
6651127 Method of detecting termination of a bus transfer operation  
A method to detect when a bus master device terminates a bus data transfer operation includes providing a first counter clocked by a first clock signal and providing a second counter clocked by a...
6643726 Method of manufacture and apparatus of an integrated computing system  
An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global...
6636947 Coherency for DMA read cached data  
A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits...
6636919 Method for host protection during hot swap in a bridged, pipelined network  
In a bridged, pipelined network (FIG. 1), a network-to-host bridge ( 140 ) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space (...
6636927 Bridge device for transferring data using master-specific prefetch sizes  
The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices...
6633943 Method and system for the simplification of leaf-limited bridges  
A method of address management in a net having a plurality of buses linked by a plurality of bus bridges where the net has only one branch bus with multiple bus bridges. A local identification...
6633944 AHB segmentation bridge between busses having different native data widths  
A bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width....
6633994 Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds  
Disclosed is a method and apparatus for optimizing communication between buses operating at different frequencies. A high speed bus provides communication between high speed devices as well as...
6631415 Method and system for providing a communication connection using stream identifiers  
A method and a system for providing a connection using a stream identifier (“id”) are disclosed. In one embodiment, the system identifies a talker node, which provides an isochronous data...
6629179 Message signaled interrupt generating device and method  
The present invention provides a bridge device and a method for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a...
6629183 Interface device for transmitting information between input/output means  
The invention relates to an interface device ( 10 ) for transmitting information between input/output means ( 12, 13 ) and application units ( 11 ) in an information and/or communication system. In...
6629000 MPEG portable sound reproducing system and a reproducing method thereof  
Disclosed is an MPEG portable sound reproducing system and a method for reproducing sound data compressed using the MPEG method. The inventive system includes power supply means for supplying...
6625683 Automatic early PCI transaction retry  
A bus bridge mechanism is provided with an automatic delayed transaction enable mode. When the automatic delayed transaction enable mode is activated, a bus master making a read request is...
6625679 Apparatus and method for converting interrupt transactions to interrupt signals to distribute interrupts to IA-32 processors  
An apparatus and method for distributing interrupts to Intel® Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system...
6622245 Firmware field programming interface and module for programming non-volatile memory on a circuit board while isolating the processor from power using expansion bus controller  
A method and apparatus for programming firmware on a circuit board without powering the entire circuit board includes a firmware interface which can be isolated from the rest of the circuit board...
6622191 Computer system  
A PCI-PCI bridge which connects a primary PCI (Peripheral Component Interconnect) bus and a secondary PCI bus comprises two physically different controllers, a primary PCI serial transfer...
6618782 Computer interconnection bus link layer  
A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of...
6611892 Network bus bridge and system  
The two-way transmissions are performed between a first bus and a usual portal of a first full-duplex 3-portal bridge and between a second bus and a usual portal of a second full-duplex 3-portal...
6611891 Computer resource configuration mechanism across a multi-pipe communication link  
Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of...
6608761 Multiple processor cards accessing common peripherals via transparent and non-transparent bridges  
In a Compact PCI system, a method and apparatus for bridging multiple PCI segments in a chassis utilizing backplane connections, instead of a front side component slot. Embodiments of the present...
6606675 Clock synchronization in systems with multi-channel high-speed bus subsystems  
A high-speed bus subsystem includes a plurality of bus channels, wherein each bus channel has an independent channel clock signal generated by an associated channel clock generator. A master device...
6604164 Computer  
Disclosed is a computer having a plurality of adapter cards which are insertable in adjacent bus segments, which are routed interleaved in the middle of a backplane and standard connectors are...
6604163 Interconnection of digital signal processor with program memory and external devices using a shared bus interface  
A circuit arrangement and method reduce the number of interconnects required for a digital signal processor by utilizing a shared bus to interconnect the digital signal processor to both a program...
Matches 401 - 450 out of 671 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 >