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6823418 Virtual PCI device apparatus and method  
Virtual PCI bus appears from the perspective of a computer program to be a part of a physical hierarchical PCI bus structure residing behind a host-to-PCI bridge. Devices that are physically...
6820161 Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects  
A method, system, and apparatus for providing data to an I/O adapter from a PCI-to-PCI bus bridge is provided. In one embodiment, once the PCI-to-PCI bus bridge receives a request for data from...
6816938 Method and apparatus for providing a modular system on-chip interface  
A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a...
6813675 Chipset with LPC interface and data accessing time adapting function  
A chipset with LPC interface and data accessing time adapting function is proposed. The chipset comprises an LPC slave controller connected to an LPC master controller in a main controller, a...
6810460 AMBA bus off-chip bridge  
An application specific integrated circuit, ASIC, having an advanced high-speed bus, AHB, operating in Advanced Microcontroller Bus Architecture, AMBA, and a bridge for connecting to an off-chip...
6807599 Computer system I/O node for connection serially in a chain to a host  
A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter...
6804736 Bus access arbitration based on workload  
A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus...
6801970 Priority transaction support on the PCI-X bus  
Support for indicating and controlling transaction priority on a PCI-X bus. Embodiments of the invention provide indicia that can be set to communicate to PCI-X-to-PCI-X bridges and Completer that...
6802016 User proximity sensor and signal processing circuitry for determining whether to power a computer on or off  
A computer system having a sensing circuit for detecting a user status and switching a computer accordingly as well as an automatic networking capability. As a user walks into a sensing area, the...
6799238 Bus speed controller using switches  
Switches are used to serially isolate connectors for peripheral devices on a bus. Bus speed is selected based on the number of peripheral devices coupled to the bus via the connectors. Switches...
6792496 Prefetching data for peripheral component interconnect devices  
Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first...
6792495 Transaction scheduling for a bus system  
A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host...
6789154 Apparatus and method for transmitting data  
In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to...
6789153 Bridge for coupling digital signal processor to on-chip bus as slave  
A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The...
6785760 Performance of a PCI-X to infiniband bridge  
Communication from a processor in a computer system to a remote input/output (I/O) unit in an expansion drawer using a Peripheral Component Interface (PCI) protocol is optimized to improve system...
6782463 Shared memory array  
Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and...
6779066 Module having application-specific program stored therein  
Once attached to a slot of a personal digital assistant PDA, a card module CM executes an application-specific program and transmits a result obtained thereby to the personal digital assistant...
6775732 Multiple transaction bus system  
This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to...
6772267 Multi-portal bridge for providing network connectivity  
Split IEEE 1394 bridges utilize individual portals or bundles of portals to communicate over a non-full-featured IEEE 1394 network such as a local or wide area network in combination with IEEE...
6772261 Interface that allows testing and using memory modules in computer systems not designed for the modules  
An interface is provided that allows testing and using in-line memory modules in computer systems not designed for the modules. In particular, an interface of the present invention comprises an...
6766404 Branch bus system for inter-LSI data transmission  
A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having...
6766399 Application programming interface for temporary release of associated file locks on storage devices  
A method is provided for use in a computer system for performing an action on a storage volume being monitored by a program. The method includes the issuing of a command to suspend the...
6763416 Capturing read data  
A bridge for use with a local bus and a memory bus capable of indicating data includes conductive traces and a local bus interface. The conductive traces are adapted to communicate indications of...
6760802 Time-out counter for multiple transaction bus system bus bridge  
The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt on reads from a second bus device if it is not given control of...
6760788 Domain validation process that is transparent to a device driver  
A computer system includes a SCSI bus for which domain validation processes can occur transparently (i.e., without device driver involvement). The system includes a SCSI bus adapter which runs...
6760852 System and method for monitoring and controlling a power-manageable resource based upon activities of a plurality of devices  
A system and method for monitoring and controlling a power-manageable resource. In one embodiment, a power manageable resource, such as a bus in a computer system, may be shareable among a number...
6757763 Universal serial bus interfacing using FIFO buffers  
An improved Universal Serial Bus interface employing FIFO buffers (300, 800) for interfacing to an application bus and a microprocessor bus, in particular, an XBUS. The interface includes a...
6751695 Bus bridge device for advanced microcontroller bus architecture (AMBA) advanced system bus (ASB) protocol  
A bus bridge device for enabling communication between a first device and a second device, wherein the first device is based on advanced microprocessor bus advanced system bus (ASB) protocol and...
6751697 Method and system for a multi-phase net refresh on a bus bridge interconnect  
A method and system for a multi-phase net refresh on a bus bridge interconnect, the interconnect comprising a number of nodes, a bus bridge, and a number of buses, are described. In one...
6748473 Split computer system including transmission of video data between plural enclosures  
A split computer (122) comprises a main module (140) remotely connected by external PCI bus (170) to a input/output (I/O) or extension module (142). The main module (140) comprises a processor...
6745272 System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system  
A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into...
6742076 USB host controller for systems employing batched data transfer  
A USB host controller for embedded systems employing batched data transfer. The system batches up to 16 individual transactions in a single batch to reduce the number and frequency of interrupts...
6738845 Bus architecture and shared bus arbitration method for a communication device  
A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are...
6732216 Peripheral switching device with multiple sets of registers for supporting an ACPI full-operation state  
In order to allow a computer system in a multiple system architectures to continue operating while another system has control over common devices, a set of registers is provided for that computer...
6732217 Control and supervisory signal transmission system  
A parent station output section changes a duty ratio between a period of a level other than a predetermined power-supply voltage level and a subsequent period of the power-supply voltage level...
6732201 Hardware speed selection behind a disk array controller  
A system has a plurality of enclosures. Each enclosure has two enclosure services modules. Each enclosure services module has an IN port and an EXPANSION port. Each enclosure services module is...
6728821 Method and system for adjusting isochronous bandwidths on a bus  
A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to...
6728820 Method of configuring, controlling, and accessing a bridge and apparatus therefor  
In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to...
6728808 Mechanism for optimizing transaction retries within a system utilizing a PCI bus architecture  
A mechanism for optimizing transaction retries within a system utilizing a peripheral component interconnect (PCI) bus architecture. Specifically, one embodiment of the present invention includes...
6725315 System and method to efficiently move data from one data bus to another data bus in a network switch  
The present invention relates to a system and method to efficiently move data from one data bus to another data bus in a network switch. The method includes generating a packet cycle on a first...
6721833 Arbitration of control chipsets in bus transaction  
A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second...
6721839 Method of mapping multiple address spaces into single PCI bus  
A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first...
6721840 Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory  
A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two...
6712277 Multiple interface memory card  
A memory card and a method for operating a memory card, the memory card comprising: a memory mass storage; a first data interface with a contacting interface and a high data transfer rate; a...
6711647 Computer system having internal IEEE 1394 bus  
A computer system that includes a computer chassis containing an IEEE 1394 bus and peripheral devices. The computer system includes a CPU, a memory, and a bridge logic unit coupling the CPU to the...
6708246 Signal processing device with bus ownership control function  
A signal processing device includes an integrated processor, a video processing unit coding a video signal, and an interface controlling a bus ownership between the integrated processor and an...
6701403 Service processor access of non-volatile memory  
Non-volatile memory access, such as firmware access by a service processor, is disclosed. The service processor asserts a controller signal to select either a first non-volatile memory, or a...
6701405 DMA handshake protocol  
A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory,...
6697921 Signal processor providing an increased memory access rate  
The bus width of the data bus among blocks for transferring data among respective blocks such as the memory control block, the error correction block, and the host I/F block is 32-bit width, and...
6697906 Semiconductor device supporting integrated data transfer bridging between CPU memory and I/O device  
A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a...