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6941405 System and method capable of offloading converter/controller-specific tasks to a system microprocessor  
Systems are provided for the offloading of protocol control and conversion information within microprocessor-based systems. A converter controller comprises a first interface and protocol, as well...
6934789 Interface, structure and method for transmitting data of PCI bus which uses bus request signal for judging whether a device supporting dual transmission mode  
A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a...
6931474 Dual-function computing system having instant-on mode of operation  
A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be...
6925517 Bus for supporting plural signal line configurations and switch method thereof  
A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer...
6920519 System and method for supporting access to multiple I/O hub nodes in a host bridge  
Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine...
6920509 Device information acquisition method, device controller, and bridge  
In a device information acquisition method, it is discriminated whether a network is constituted by a plurality of buses or a single bus. A bus ID assigned to each of remote buses is acquired....
6915369 Modular and scalable system bus structure  
A high-bandwidth data transfer apparatus that is suitable for modular and scalable processing systems is disclosed. In one embodiment, the data transfer apparatus includes a local bus between each...
6910093 Method of pacing and disconnecting transfers on a source strobed bus  
A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a...
6910090 Maintaining communications in a bus bridge interconnect  
A method of maintaining communications in a bus bridge interconnect including a plurality of buses linked by at least one bus bridge. The method includes receiving a change indication signal from...
6910113 Executing large device firmware programs  
A processor-based system includes a system firmware program (e.g., the system basic input/output system (BIOS)) to execute a device firmware program (e.g., a device driver) stored on a storage...
6909952 Device for controlling/regulating the operational sequences in a motor vehicle  
A device for controlling/regulating the operational sequences in a motor vehicle. The device has a number of arrangements for control/regulation. Each of the arrangements includes a processor...
6904486 32 bit generic bus interface using read/write byte enables  
A display controller configured to communicate with a microprocessor is provided. The display controller includes a memory core for storing image data to be displayed and a register set containing...
6898684 Control chip with multiple-layer defer queue  
A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC...
6898658 Method to prevent net update oscillation  
A method for preventing net update oscillation of a bus bridge by competing net update messages is presented. The method includes the steps of (a) determining whether a particular portal is a...
6898659 Interface device having variable data transfer mode and operation method thereof  
An interface device according to the present invention interfaces with a host by an m-bit unit. A flag signal generator circuit generates a mode flag signal indicating whether a data transfer mode...
6886051 Device discovery method and apparatus  
A method of discovering and assigning unique addresses to devices connected by at least one expander in a system is provided. The method includes locating each expander in the system. Also,...
6883057 Method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0  
A method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0 is disclosed. The PCI-to-PCI bridge function is implemented in PCI devices using...
6883051 Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses  
In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave...
6880034 Medical device with dual communications bus  
A medical appliance having an auxiliary computer system in addition to its action computer system, and further having two communications buses. The auxiliary computer system independently monitors...
6877039 Simplified pipeline writes over a network  
A system and method are provided for efficiently writing data from one bus device to another bus device across a network. Data packets to be transmitted are ordered and assigned sequence numbers...
6871253 Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection  
A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by...
6868459 Methods and structure for transfer of burst transactions having unspecified length  
Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst...
6868468 Switchable hot-docking interface for a portable computer for hot-docking the portable computer to a docking station  
A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more...
6868469 Data bridge and bridging  
The present invention is in the field of bridging transactions from one bus to a second bus. More particularly, embodiments of the present invention can enhance an interface between two buses by...
6865618 System and method of assigning device numbers to I/O nodes of a computer system  
A system and method of assigning device numbers to a plurality of I/O nodes of a computer system. Each of the plurality of input/output nodes is initialized to a common default device number. The...
6862647 System and method for analyzing bus transactions  
A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor....
6862646 Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain  
The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as...
6862645 Computer system  
A computer system is arranged to provide protection against faults. The computer system comprises a plurality of processing sets (14, 16), each having at least one processor (52) and a bridge (12)...
6859852 Immediate grant bus arbiter for bus system  
The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect two separate busses together and...
6857040 Bi-directional bus bridge in which multiple devices can assert bus concurrently  
A bridge device couples together two buses in which more than one device at a time can assert a bus signal. The bridge includes comparators to drive or assert signals on one bus only if the signal...
6857033 I/O node for a computer system including an integrated graphics engine and an integrated I/O hub  
An I/O node for a computer system including an integrated graphics engine and integrated I/O hub. An input/output node that is implemented on an integrated circuit chip includes a transceiver...
6851004 Adaptive retry mechanism  
An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency...
6848015 Arbitration technique based on processor task priority  
A computer system including multiple CPUs inform other logic in a computer system as to the priority level (e.g., task priority) associated with the CPU or software executing thereon. The logic...
6845413 Switchover device and information recording/reproducing apparatus having the switchover device  
An improved switchover device includes input terminals connected with information sources, first and second output terminals connected with information processing devices, switching elements for...
6842817 Method for generating configuration tables and for forwarding packets through a network  
A method performed by a computer system that includes a host processor coupled to a first bus, a first switch coupled to the first bus and a second bus, a second switch coupled to the second bus...
6839788 Bus zoning in a channel independent storage controller architecture  
A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), described. The network storage controller...
6839857 Interrupt controller in an interface device or information processing system  
There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is...
6836813 Switching I/O node for connection in a multiprocessor computer system  
A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip....
6834320 Optimized bus connection for managing bus transactions  
For optimization of the mode of operation of processor systems, there is proposed a bus connection which divides bus transactions substantially into transactions that must be executed in strictly...
6832269 Apparatus and method for supporting multiple graphics adapters in a computer system  
An apparatus and a method for supporting coexistence of an external AGP graphics adapter with an embedded graphics adapter. The embedded graphics adapter may be regarded as a PCI device, and the...
6832282 System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system  
A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP...
6829672 Electronic flash memory external storage method and device  
An electronic flash memory external storage method and device for data processing system, comprising firmware which directly controls the access of electronic storage media and implements standard...
6829665 Next snoop predictor in a host controller  
A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which...
6829669 Bus bridge interface system  
A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data...
6826628 PCI-PCMCIA smart card reader  
A method and apparatus is disclosed for implementing an integrated video card and smart card reader. A single processor is used to perform both video and smart card reader functions. The processor...
6823419 Method and apparatus for inhibiting a selected IDE command  
An interface circuit replaces a selected IDE command received from a host computer with an invalid command and routes the invalid command to a data storage device. In this manner, the interface...
6823420 Entertainment apparatus  
An entertainment apparatus comprising a peripheral device and a controller for controlling the peripheral device. The peripheral device and the controller are connected each other by an address...
6823421 Method, apparatus, and system for maintaining conflict-free memory address space for input/output memory subsystems  
According to one embodiment of the present invention, an apparatus is provided which includes a first address translation unit and a second address translation unit. The first address translation...
6823409 Coherency control module for maintaining cache coherency in a multi-processor-bus system  
A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.
6823417 Memory controller for memory card manages file allocation table  
A memory card controller controls the file allocation table and file system structures of a memory card, in order to speed up data transfer to and from the memory card and a host device, such as a...