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5029074 |
Bus adapter unit for digital processing system
A digital data processing system includes a plurality of processing subsystems, each including an adapter for enabling transfers between the resident subsystem and other subsystems. The adapter...
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4974144 |
Digital data processor with fault-tolerant peripheral interface
A fault-tolerant digital data processing system comprises a first input-output controller which communicates with at least one peripheral device over a peripheral device bus having first and second...
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4974153 |
Repeater interlock scheme for transactions between two buses including transaction and interlock buffers
A system for implementing a repeater interlock scheme between a first and a second bus utilizes two repeaters. The first repeater coupled to the first bus includes an interlock state bit which is...
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4954949 |
Universal connector device for bus networks in host computer/co-processor computer system
A connector device for use in communication of data between the central processing unit (CPU) bus of a host computer system and the CPU bus of a co-processor computer system, between the CPU bus of...
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4937785 |
Visual signal processing backplane bus
A custom bus for a visual signal (image) processing system which can interface with a standard high speed industrial standard computer bus and requires minimal interface circuitry. Eight lines are...
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4864496 |
Bus adapter module for interconnecting busses in a multibus computer system
A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the...
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4695952 |
Dual redundant bus interface circuit architecture
An asynchronous bus interface circuit manages the transfer of messages between a host processor memory, and one of two redundant serial data buses by separately processing command words thereby...
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4675803 |
System for processing information
A system is provided to receive and process information including a processor, an operator station and an interconnect processor. The interconnect processor is coupled to the processor by a first...
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4570220 |
High speed parallel bus and data transfer method
A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present...
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4476524 |
Page storage control methods and means
The embodiment provides an independent data bus path between a random access page storage (PS), and a main storage (MS), wherein this independent data bus does not pass through any channel...
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4470113 |
Information processing unit
An information processing unit, such as a central processor, microprocessor or one-chip microcomputer, which can be used as either a master unit or a slave unit yet does not require the provision...
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4384327 |
Intersystem cycle control logic
A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein...
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4384322 |
Asynchronous multi-communication bus sequence
An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication...
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4300194 |
Data processing system having multiple common buses
Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the...
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4296469 |
Execution unit for data processor using segmented bus structure
A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to...
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4234919 |
Intersystem communication link
A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing...
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4205373 |
System and method for accessing memory connected to different bus and requesting subsystem
A method and system for accessing a memory subsystem from a requesting subsystem connected to a first bus. The memory subsystem is connected to a second bus. A pair of adaptors coupled to each...
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4047162 |
Interface circuit for communicating between two data highways
An interface circuit for use in a data transmission system is designed to be used not only between a highway and a device but also to link highways and can be commanded to enter a status in which...
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4041472 |
Data processing internal communications system having plural time-shared intercommunication buses and inter-bus communication means
A memory subsystem is connected to an addressable port on one bus and a non-memory subsystem is connected to an addressable port on another bus. Access to the memory is achieved by the non-memory...
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4016546 |
Bus switch coupling for series-coupled address bus sections in a microprocessor
A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control...
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3215987 |
Electronic data processing
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