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7174408 |
Interface for serial data communication
An interface connectable as a default host to a peripheral or as a default peripheral to a host, for serial data communication between host and peripheral during a session, and comprising:...
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7173964 |
Method for detecting data transmission rate of USB controller by using USB device
A method is provided for detecting the data transmission rate of a USB controller by using a USB device having at least one program storage device. An IRQ signal of a timer is activated through a...
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7174395 |
Communication interface method and device utilizing direct memory access data transfer
In asynchronous communication, an efficient data transfer can be performed between an external bus and an internal bus. A packet obtained from the external bus by the asynchronous communication is...
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7174411 |
Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit...
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7174550 |
Sharing communications adapters across a plurality of input/output subsystem images
A communications adapter is shared by a plurality of input/output (I/O) subsystem images of an I/O subsystem of a central processing complex. To enable the sharing, the communications adapter is...
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7174400 |
Integrated circuit device that stores a value representative of an equalization co-efficient setting
An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an...
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7171504 |
Transmission unit
A transmission unit that improves communication quality by making effective use of a line to a blocked port in compliance with a spanning tree protocol. Bridges have bridge ports and communicate at...
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7171510 |
On-chip observability buffer to observer bus traffic
The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without...
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7171506 |
Plural interfaces in home network with first component having a first host bus width and second component having second bus width
Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes).
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7171540 |
Object-addressed memory hierarchy that facilitates accessing objects stored outside of main memory
One embodiment of the present invention provides an object-addressed memory hierarchy that is able to access objects stored outside of main memory. During operation, the system receives a request...
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7171505 |
Universal network interface connection
An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The...
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7167940 |
Data processing method, data processing apparatus, communications device, communications method, communications protocol and program
To prevent a command from being unsmoothly issued when a communications channel (LUN) from a conventional initiator to a target enters communications disabled state for any reason there is...
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7167939 |
Asynchronous system bus adapter for a computer system having a hierarchical bus structure
A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system...
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7167938 |
Data transfer memory
A data transfer memory for reducing the number of components in an electronic module. A master controller circuit provides a transfer start command to a master clock signal generator circuit when...
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7165136 |
System and method for managing bus numbering
Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a...
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7162615 |
Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch
Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to...
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7162553 |
Correlating high-speed serial interface data and FIFO status signals in programmable logic devices
Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to...
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7159059 |
Ultra-modular processor in lattice topology
A Modular Operating Topology Element (MOTE), within a software-latticed network, implements ultra-concurrent operation of a plurality of such MOTEs, as single miniaturized packages, e.g., Compact...
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7159061 |
Link layer device with configurable address pin allocation
Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device...
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7159062 |
Electronic shelf unit with management function performed by a common shelf card with the assistance of an auxiliary interface board
An electronic shelf includes a plurality of system circuit boards including a first system circuit board containing a first central processing unit (CPU) providing decision-making intelligence for...
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7159052 |
Configurable architecture for virtual socket client to an on-chip bus interface block
An interface block provides an interface between an internal bus of an integrated circuit and a socket of a logic block. The interface block includes a synchronization module that performs any...
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7159065 |
Method for issuing vendor specific requests for accessing ASIC configuration and descriptor memory while still using a mass storage class driver
A bridge-chip may interface a Universal Serial Bus to a mass storage device. Communications of the universal serial bus may be examined to determine a command block wrapper (CBW) of a bulk...
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7155546 |
Multiple physical interfaces in a slot of a storage enclosure to support different storage interconnect architectures
Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the...
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7155553 |
PCI express to PCI translation bridge
A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is treated as a virtual port for the...
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7155554 |
Methods and apparatuses for generating a single request for block transactions over a communication fabric
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block...
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7152129 |
Apparatus having an inter-module data transfer confirming function, storage controlling apparatus, and interface module for the apparatus
In a storage controlling apparatus controlling an access from a host to a disk apparatus, for example, when a data transfer confirmation flag set in a data transfer descriptor is “ON”, a data...
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7152128 |
General input/output architecture, protocol and related methods to manage data integrity
An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general...
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7152136 |
Implementation of PCI express
Methods and apparatus are provided for providing PCI Express support. A device includes a hard-coded transceiver configured to support protocols such as Fibre Channel and the 10 Gigabit Attachment...
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7152125 |
Dynamic master/slave configuration for multiple expansion modules
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
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7149823 |
System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur
A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the...
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7149838 |
Method and apparatus for configuring multiple segment wired-AND bus systems
A special bus master, called a configuration host, “walks” a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the...
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7146448 |
Apparatus and method for adopting an orphan I/O port in a redundant storage controller
A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two...
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7146441 |
SRAM bus architecture and interconnect to an FPGA
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of...
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7146480 |
Configurable memory system
A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality...
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7142443 |
Reduced data line pre-fetch scheme
A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops...
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7143226 |
Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link
The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various...
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7143225 |
Apparatus and method for viewing data processor bus transactions on address pins during memory idle cycles
A processing system comprising: i) a processor core; ii) a memory; iii) a plurality of peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the peripheral...
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7143227 |
Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller
A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write...
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7139861 |
Input/output unit access switching system and method
An I/O unit access switching system and its method are implemented on a plurality of servers respectively having a baseboard management controller (BMC) and an intelligent platform management...
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7136952 |
Method for programming firmware hubs using service processors
A method and system that enables a service processor to program a system resource. The service processor uses a JTAG Bus to request a system processor to enter into probe mode. Once in probe mode,...
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7136947 |
System and method for automatically synthesizing interfaces between incompatible protocols
A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to...
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7136950 |
Multifunction passive adaptor for flash media cards
The present invention enables the use of a single passive adaptor ( 1500, 1800 ) for multiple types of flash media cards. The present invention provides this by implementing form factors with a...
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7132927 |
Universal serial bus extension cable
A controller capable of being located in a peripheral device or host, is capable of engaging in data communications with a host or peripheral device over a power line. A power line interface...
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7133955 |
System and method for selecting fabric master
A system and method for selecting a fabric master using an announce phase and a own phase. During an announce phase a candidate master interrogates its Node Path Identifier to ensure that it has...
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7133944 |
Media access controller with power-save mode
There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all...
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7134056 |
High-speed chip-to-chip communication interface with signal trace routing and phase offset detection
A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle,...
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7133956 |
Electronic device with serial ATA interface and signal amplitude adjusting method
The CPU of an electronic device generates a parameter for determining the amplitude of a serial data signal when it is output from an output device to a serial ATA bus. The parameter indicates a...
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7133954 |
Data bus system for micro controller
Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system...
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7133942 |
Sequence-preserving multiprocessing system with multimode TDM buffer
A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and...
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7133953 |
Data transmission device used to forward data received at a first device for a second device to the second device
A data transmission device is used to forward data that have been received from a first device, and are intended for a second device, to the second device. The data transmission device described...
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