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7362697 |
Self-healing chip-to-chip interface
A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed...
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7363396 |
Supercharge message exchanger
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store...
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7360004 |
Powering a notebook across a USB interface
A laptop computer and mating docking station where the docking station provides power to the laptop computer over power rails of the Universal Serial Bus (USB) interface. The laptop computer has...
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7360010 |
Method and apparatus for storage command and data router
An interconnecting unit and method for data communication between a plurality of computer hosts and a plurality of storage devices. The interconnecting unit couples the hosts to the storage devices...
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7359997 |
USB data transfer control device including first and second USB device wherein destination information about second device is sent by first device
A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information...
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7359993 |
Method and apparatus for interfacing external resources with a network element
External resources may be interfaced with a network element using an intelligent interface including an independent processing environment to enable the operational capabilities of the network...
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7360005 |
Software programmable multiple function integrated circuit module
An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input...
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7356629 |
Conveying data between computing devices
Techniques are provided for conveying data between computing devices. In certain implementations, a system and method for conveying data between computing devices include the capability to, at a...
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7356632 |
Data memory controller that supports data bus invert
The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a...
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7356555 |
In-protocol impedance compensation control
One embodiment of a technique for performing impedance compensation update operations without causing potential data corruption problems includes taking advantage of protocol idle periods, where...
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7353302 |
Selectable communication control between devices communicating using a serial attached SCSI (SAS) protocol
In one embodiment, an apparatus may include a plurality of ports capable of being coupled to a plurality of devices via an associated plurality of communication links, the links being compliant...
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7353313 |
General input/output architecture, protocol and related methods to manage data integrity
An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g.,...
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7353308 |
Avoiding oscillation in self-synchronous bi-directional communication system
In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a...
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7350161 |
System design tools
A system design method for designing bus-based systems is described. The method includes automatically defining an allowed set of parameter values for the system components concerned.
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7349999 |
Method, system, and program for managing data read operations on network controller with offloading functions
Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one...
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7350012 |
Method and system for providing fault tolerance in a network
A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant...
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7346723 |
Slave devices and methods for operating the same
A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be...
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7346051 |
Slave device, master device and stacked device
A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of...
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7346724 |
Enabling multiple ATA devices using a single bus bridge
Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that...
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7346722 |
Apparatus for use in a computer systems
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module...
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7346718 |
Autonomous integrated-circuit card
An autonomous integrated circuit card includes a logic external communication interface which directly communicates with a communication device connected to an integrated circuit card terminal main...
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7343458 |
Memory channel with unidirectional links
Memory interface apparatus and methods utilize unidirectional links. An embodiment of a memory apparatus may include a first redrive circuit to receive a first signal from a first unidirectional...
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7343451 |
Disk array device and remote copying control method for disk array device
Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional...
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7343440 |
Integrated circuit with a scalable high-bandwidth architecture
An integrated circuit component is provided comprising logic capable of being configured to interface with a first companion integrated circuit and to receive information that is communicated from...
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7340542 |
Data processing system with bus access retraction
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access...
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7340555 |
RAID system for performing efficient mirrored posted-write operations
A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a...
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7340552 |
Bus control system
In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source...
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7340548 |
On-chip bus
This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip...
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7337259 |
Smart card virtual hub
A smart card virtual hub combines an ISO7816 compliant smart card reader interface with a USB hub that provides one or more attachment points for connection of devices to the USB bus, thereby...
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7337258 |
Dynamically allocating devices to buses
Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on...
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7337261 |
Memory apparatus connectable to a host system having a USB connector
An integrated semiconductor memory device for use within an integrated USB memory apparatus has a controller, a flash memory in communication with the controller, a USB interface circuit in...
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7337249 |
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by...
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7334233 |
Method and apparatus for multiple slaves to receive data from multiple masters in a data processing system
A method, apparatus, and computer instructions for managing requests for data by processes in a data processing system. Requests for data from the processes in slave mode are tracked. Data received...
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7334234 |
Method and apparatus for transferring data to virtual devices behind a bus expander
A method, apparatus, and computer instructions for transferring data from a master to a set of applications executing on a slave. Data is received from a master at a device driver in the slave. The...
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7334071 |
Expansion of cross-domain addressing for PCI-express packets passing through non-transparent bridge
A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to...
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7330924 |
Network media access controller embedded in a programmable logic device—physical layer interface
An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical...
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7330916 |
Graphic controller to manage a memory and effective size of FIFO buffer as viewed by CPU can be as large as the memory
A system for providing a command stream that includes a controller chip is disclosed. The controller chip includes an engine operative to manage a memory. The engine includes an interface. A...
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7328298 |
Apparatus and method for controlling I/O between different interface standards and method of identifying the apparatus
According to the present invention, an input/output controller connected between an interface connection port of an information processing apparatus and a network device so as to connect the...
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7328289 |
Communication between processors
A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common...
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7328288 |
Relay apparatus for relaying communication from CPU to peripheral device
In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information...
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7327581 |
Circuit device
A circuit device includes plural semiconductor circuit devices that are formed on independent substrates, respectively, and communicate with each other. Each of the semiconductor circuit devices...
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7325087 |
Using a processor to program a semiconductor memory
A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate...
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7325231 |
Method and related device for updating firmware code stored in non-volatile memory
A non-volatile memory is installed in an electronic device. A method for updating a firmware code stored in a non-volatile memory includes: providing an updating control unit having a command set;...
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7321948 |
Highly available system test mechanism
Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding...
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7321938 |
Data transfer apparatus, network system, and data transfer method
Whether the node to which data has been sent is connected to a bus is determined according to destination information, and, when it is determined that the node is not connected to the bus,...
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7320043 |
Split computer architecture to separate user and processor while retaining original user interface
A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on...
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7315914 |
Systems and methods for managing virtualized logical units using vendor specific storage array commands
Systems and methods are provided for executing a vendor specific command in a storage area network including a plurality of data storage volumes and at least one host. In one embodiment, a system...
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7315456 |
Configurable IO subsystem
An enclosure for an input-output (IO) subsystem comprises: a backplane; a plurality of first slots for accepting corresponding IO option modules; a second slot for accepting an IO controller...
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7313660 |
Data stream frequency reduction and/or phase shift
A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input...
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7313641 |
Inter-processor communication system for communication between processors
A system ( 15 ) comprising at least two integrated processors (P 1 and P 2 ). These two processors (P 1 and P 2 ) are operably connected via a communication channel ( 17 ) for exchanging...
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