Matches 1 - 50 out of 146 1 2 3 >
Match Document Document Title
7613863 High-speed data readable information processing device  
A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF...
7606961 Computer system and data pre-fetching method  
A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a...
7568055 Data processing apparatus for selecting either a PIO data transfer method or a DMA data transfer method  
The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit...
7568054 Duplicate synchronization system and method of operating duplicate synchronization system  
The duplicate synchronization system has: a first system; and a second system operating in synchronization with the first system. The first and the second systems are connected to each other. The...
7519754 Hard disk drive cache memory and playback device  
A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function...
7493424 Network storage system with shared software stack for LDMA and RDMA  
A network storage system includes a non-volatile memory to store data including a log of received data access requests, and a cluster interconnect adapter through which to send data to a cluster...
7475182 System-on-a-chip mixed bus architecture  
A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could...
7464199 Method, system, and program for handling Input/Output commands  
Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device...
7464197 Distributed direct memory access for systems on chip  
A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct...
7451250 Methods and apparatus for providing automatic high speed data connection in portable device  
In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard drive (HDD), and a FireWire port,...
7444441 Device including means for transferring information indicating whether or not the device supports DMA  
A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct...
7404015 Methods and apparatus for processing packets including accessing one or more resources shared among processing engines  
Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to...
7380115 Transferring data using direct memory access  
A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command...
7370131 High-speed data readable information processing device  
A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF...
7350015 Data transmission device  
A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it...
7313641 Inter-processor communication system for communication between processors  
A system ( 15 ) comprising at least two integrated processors (P 1 and P 2 ). These two processors (P 1 and P 2 ) are operably connected via a communication channel ( 17 ) for exchanging...
7302699 Logged-in device and log-in device  
A management agent ME 1 of a target T 1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T 1 ...
7259876 Image processing apparatus, and, control method and control device therefor  
A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data...
7228367 Direct memory access controller for carrying out data transfer by determining whether or not burst access can be utilized in an external bus and access control method thereof  
An address region of an internal bus wherein a burst access can be utilized in an external bus is set in an address table. A DMA control unit determines whether or not a burst access can be...
7219169 Composite DMA disk controller for efficient hardware-assisted data transfer operations  
In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a...
7200693 Memory system and method having unidirectional data buses  
A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from...
7177960 Mobile terminal  
To display a horizontally oblong movie on a vertically oblong display portion, the movie may be displayed with being rotated 90 degrees by a CPU while the display portion is held in an orientation...
7155572 Method and apparatus for injecting write data into a cache  
A data processing system ( 100, 600 ) has a memory hierarchy including a cache ( 124, 624 ) and a lower-level memory system ( 170, 650 ). A data element having a special write with inject attribute...
7149823 System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur  
A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the...
7130933 Method, system, and program for handling input/output commands  
Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device...
7127534 Read/write command buffer pool resource management using read-path prediction of future resources  
A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is...
7099345 Method and system for buffering a data packet for transmission to a network  
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory....
7035981 Asynchronous input/output cache having reduced latency  
The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication...
7003593 Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port  
A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with,...
6988167 Cache system with DMA capabilities and method for operating same  
In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data...
6986020 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
6978322 Embedded controller for real-time backup of operation states of peripheral devices  
An embedded controller includes a central processing unit, a memory interface for interface with an external memory, and a function block or peripheral device with a register for storing operation...
6941390 DMA device configured to configure DMA resources as multiple virtual DMA channels for use by I/O resources  
Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory configured...
6922741 Method and system for monitoring DMA status  
Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers,...
6898657 Autonomous signal processing resource for selective series processing of data in transit on communications paths in multi-processor arrangements  
A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal...
6880035 Electronic bus control device with a parallel databus and a method for the operation of the bus control device  
An electronic control device with a parallel databus and a plurality of assemblies connected to the databus. The assemblies each include a processor and a memory device and are connected to the...
6868486 Providing multiple memory controllers on a memory bus  
A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority...
6865638 Apparatus and method for transferring multi-byte words in a fly-by DMA operation  
An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner...
6859845 System for resolving conflicts due to simultaneous media streams and method thereof  
A system and methods are provided for resolving resource conflicts related to processing multiple media streams on a single media device. An audio/video (A/V) server is used to interconnect a...
6820143 On-chip data transfer in multi-processor system  
A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor....
6810444 Memory system allowing fast operation of processor while using flash memory incapable of random access  
A DMA control circuit controls DMA transfer between a flash memory and a main memory. An S/P bus conversion circuit converts serial data output from the flash memory into parallel data and outputs...
6801958 Method and system for data transfer  
According to one embodiment of the present invention, a system ( 10 ) for data transfer is disclosed that comprises a transfer memory ( 24 ) having one or more buffers ( 40, 42, 44, 46 , and 48 )....
6785743 Template data transfer coprocessor  
The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based...
6785284 Interleavement for transport of frames and cells  
A DMA system includes a plurality of transmit-receive pairs ( 102, 104 ) for communicating on a bus. A DMA controller ( 108 ) supervises bus handling. The DMA controller ( 108 ) includes a priority...
6782463 Shared memory array  
Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and...
6754733 Shared memory architecture for increased bandwidth in a printer controller  
A printer controller for processing print data includes a data processor, direct memory access controller, first and second memories with corresponding first and second transfer data busses. A bus...
6745301 Microcontroller programmable method for accessing external memory in a page mode operation  
A microcontroller and method for executing instructions from an 8051 instruction set are disclosed. The microcontroller includes first and second input/output (I/O) ports that are controlled such...
6738837 Digital system with split transaction memory access  
A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system...
6708244 Optimized I2O messaging unit  
A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more...
6665759 Method and apparatus to implement logical partitioning of PCI I/O slots  
A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a...
Matches 1 - 50 out of 146 1 2 3 >