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Document Title |
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7577831 |
Relocating of system management interface code within an information handling system
A method for relocating system management interface code in an information handling system which includes extracting a relocation table from the system management interface code, inserting a...
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7549039 |
Generating an interrupt in a system having plural partitions that share a resource
A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is...
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7516252 |
Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment
Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and...
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7503049 |
Information processing apparatus operable to switch operating systems
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
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7496706 |
Message signaled interrupt redirection table
In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also...
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7493435 |
Optimization of SMI handling and initialization
A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use...
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7480755 |
Trap mode register
Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables...
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7457903 |
Interrupt controller for processing fast and regular interrupts
A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is...
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7444449 |
Method, computer program product and computer system for controlling execution of an interruption routine
A method, a computer program product and a computer system for controlling the execution of an interruption routine for interrupting an active application. The computer system may include a first...
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7433985 |
Conditional and vectored system management interrupts
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode...
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7424563 |
Two-level interrupt service routine
A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt...
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7415557 |
Methods and system for providing low latency and scalable interrupt collection
A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an...
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7398343 |
Interrupt processing system
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding...
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7395362 |
Method for a slave device to convey an interrupt and interrupt source information to a master device
A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with...
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7370130 |
Core logic device of computer system
A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC...
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7363407 |
Concurrent arbitration of multidimensional requests for interrupt resources
The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration...
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7353312 |
Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device
A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU,...
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7328295 |
Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources
An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an...
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7325084 |
Messages signaling interrupt (MSI) processing system
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding...
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7302690 |
Method and apparatus for transparently sharing an exception vector between firmware and an operating system
A method, apparatus and computer instructions for handling exception vectors by firmware. An exception vector is identified to form an identified exception vector when control is passed from an...
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7287112 |
Dynamic reconfiguration interrupt system and method
The present invention system and method enables dynamic reconfiguration of an electronic device with appropriate interrupts in a convenient and efficient manner. A plurality of internal...
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7281073 |
Method for controlling interrupts and auxiliary control circuit
An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt...
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7257658 |
Message based interrupt table
An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The...
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7249211 |
System and method for interrupt handling
A system, methodology and/or computer architecture that facilitates processing device interrupts (including level-triggered interrupts) in a user-mode process is provided. The kernel interrupt...
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7240137 |
System and method for message delivery across a plurality of processors
A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue...
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7222251 |
Microprocessor idle mode management system
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated...
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7222203 |
Interrupt redirection for virtual partitioning
The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical...
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7209994 |
Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests
In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is...
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7209993 |
Apparatus and method for interrupt control
An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system...
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7200700 |
Shared-IRQ user defined interrupt signal handling method and system
A shared-IRQ user-defined interrupt signal handling method and system is proposed, which is designed for use with a computer platform to allow a group of peripheral devices connected to an...
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7197586 |
Method and system for recording events of an interrupt using pre-interrupt handler and post-interrupt handler
A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’...
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7165135 |
Method and apparatus for controlling interrupts in a secure execution mode-capable processor
A method is provided for controlling interrupts in a secure execution mode-capable processor. The method includes detecting an interrupt and performing a predetermined routine in response to...
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7149831 |
Batch processing of interrupts
A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working...
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7143197 |
Method and system for monitoring a telecommunications signal transmission link
A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to...
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7139857 |
Method and apparatus for handling interrupts
An apparatus and method for handling an interrupt are disclosed. In one embodiment, a processor may receive an interrupt request corresponding to a particular interrupt. The particular interrupt...
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7124225 |
Method and apparatus for multi-interrupt controller for reducing hardware interrupts to DSP
The present inventions provide a controlling device for reducing external interrupts for a processor and the method thereof in a real time system. The controlling device decides whether it should...
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7080179 |
Multi-level interrupts
Multiple levels of interrupts to be utilized in a computer system, which allows, for example, an interrupt with an interrupt level associated with an application to be distinct from an interrupt...
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7058557 |
Method for functional verification of hardware design
A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test...
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7054974 |
System for end of interrupt handling
An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector...
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7048877 |
Efficiently supporting interrupts
A method, system, and article of manufacture to efficiently support interrupts of a computer system. A message-based interrupt from a device of the computer system is intercepted. A fake line-based...
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7043729 |
Reducing interrupt latency while polling
Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system...
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7017029 |
Coprocessor instruction loading from port register based on interrupt vector table indication
An interface source system providing at least two paths to load an instruction decode register of a coprocessor is disclosed. The interface source system includes an instruction port register, an...
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7010671 |
Computer system and method for executing interrupt instructions in two operating modes
A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier...
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7007119 |
System and method for supporting split transactions on a bus
System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node....
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7000051 |
Apparatus and method for virtualizing interrupts in a logically partitioned computer system
A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical...
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RE38927 |
System management memory for system management interrupt handler independent of BIOS and operating system
A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system...
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6973522 |
Microcomputer with program-revision ability
A microcomputer has a ROM with pre-stored programs, a RAM storing a revision program for executing an interruption-processing, and a program counter in which an address is successively renewed...
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6968410 |
Multi-threaded processing of system management interrupts
An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected...
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6952749 |
Multiprocessor interrupt handling system and method
An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the...
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6944699 |
System and method for facilitating context-switching in a multi-context computer system
A virtual machine monitor (VMM) is included in a computer system that has a protected host operating system (HOS). A virtual machine running at least one application via a virtual operating system...
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