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8180944 |
Guest interrupt manager that records interrupts for guests and delivers interrupts to executing guests
In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is...
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8145820 |
Multiprocessor system and computer program product
In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for...
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8135894 |
Methods and systems for reducing interrupt latency by using a dedicated bit
A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to...
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8074109 |
Third-party voting to select a master processor within a multi-processor computer
Techniques are described of using votes of third-party components to select a master processor from a plurality of redundant processors. A master processor and a standby processor maintain...
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8060716 |
Information processing device for securely processing data that needs to be protected using a secure memory
To aim to provide an information processing device capable of improving a processing capability and securely handling programs and data to be protected. According to a system LSI including a...
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8051235 |
Conditional back-to-back interrupt vectoring
Upon execution of an interrupt return (IRET) instruction when a second interrupt is pending, rather than popping a stack, obtaining processor state information, and then pushing the state...
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7996595 |
Interrupt arbitration for multiprocessors
Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level...
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7953915 |
Interrupt dispatching method in multi-core environment and multi-core processor
Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are...
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7917657 |
Method and system for monitoring a telecommunications signal transmission link
A system including an event monitor for monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data...
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7913018 |
Methods and apparatus for halting cores in response to system management interrupts
A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with...
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7913017 |
Embedded system and interruption handling method
An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In...
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7873770 |
Filtering and remapping interrupts
In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base...
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7870320 |
Interrupt controller for prioritizing interrupt requests in an embedded disk controller
An interrupt controller for a disk controller includes an interrupt scanner module that receives a plurality of interrupt requests (IRQs) from a plurality of corresponding interrupt sources,...
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7793091 |
Method, computer-readable media, devices and systems for loading a selected operating system of interest
Representative of the various embodiments is a method for implementation during a computer's boot sequence to load a selected operating system (OS) of interest. For purposes of such a method the...
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7783811 |
Efficient interrupt message definition
An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory...
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7769937 |
Data processing system with interrupt controller and interrupt controlling method
A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data...
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7752370 |
Splitting one hardware interrupt to multiple handlers
A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and...
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7739438 |
Method for priority-encoding interrupts and vectoring to interrupt code
A method for interrupt priority encoding and vectoring begins with reading pending interrupt bits from an interrupt status register. An entry in a table is located using the pending interrupt bits....
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7734905 |
System and method for preventing an operating-system scheduler crash
System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated...
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7730250 |
Interrupt control circuit, circuit board, electro-optic device, and electronic apparatus
An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that...
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7725637 |
Methods and apparatus for generating system management interrupts
A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management...
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7702836 |
Parallel processing device and exclusive control method
To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An...
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7694055 |
Directing interrupts to currently idle processors
Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of...
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7689748 |
Event handler for context-switchable and non-context-switchable processing tasks
Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed...
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7673086 |
Retrieving lock attention data using an attention connection path selected from a group of attention connection paths associated with a host
Provided are techniques for retrieving lock attention data. A group of attention connection paths configured to transmit lock attention interrupts and lock attention data between the host and the...
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7665088 |
Context-switching to and from a host OS in a virtualized computer system
The invention virtualizes a computer that includes a host computer system, which comprises a processor, memory, and physical system devices. A conventional operating system (referred to below as...
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7661105 |
Exception types within a secure processing system
An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode...
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7647600 |
Method for the direct call of a function by a software module by means of a processor with a memory-management unit (MMU)
System and method for direct call of a target function by a start function by means of a processor with a memory management unit (MMU) in a computer operated by an operating system. A first task...
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7577831 |
Relocating of system management interface code within an information handling system
A method for relocating system management interface code in an information handling system which includes extracting a relocation table from the system management interface code, inserting a...
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7549039 |
Generating an interrupt in a system having plural partitions that share a resource
A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is...
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7516252 |
Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment
Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and...
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7503049 |
Information processing apparatus operable to switch operating systems
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed by...
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7496706 |
Message signaled interrupt redirection table
In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also...
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7493435 |
Optimization of SMI handling and initialization
A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use...
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7480755 |
Trap mode register
Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables...
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7457903 |
Interrupt controller for processing fast and regular interrupts
A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is...
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7444449 |
Method, computer program product and computer system for controlling execution of an interruption routine
A method, a computer program product and a computer system for controlling the execution of an interruption routine for interrupting an active application. The computer system may include a first...
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7433985 |
Conditional and vectored system management interrupts
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode...
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7424563 |
Two-level interrupt service routine
A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt...
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7415557 |
Methods and system for providing low latency and scalable interrupt collection
A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an...
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7398343 |
Interrupt processing system
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding...
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7395362 |
Method for a slave device to convey an interrupt and interrupt source information to a master device
A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with...
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7370130 |
Core logic device of computer system
A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC...
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7363407 |
Concurrent arbitration of multidimensional requests for interrupt resources
The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration...
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7353312 |
Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device
A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU,...
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7328295 |
Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources
An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an...
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7325084 |
Messages signaling interrupt (MSI) processing system
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding...
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7302690 |
Method and apparatus for transparently sharing an exception vector between firmware and an operating system
A method, apparatus and computer instructions for handling exception vectors by firmware. An exception vector is identified to form an identified exception vector when control is passed from an...
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7287112 |
Dynamic reconfiguration interrupt system and method
The present invention system and method enables dynamic reconfiguration of an electronic device with appropriate interrupts in a convenient and efficient manner. A plurality of internal...
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7281073 |
Method for controlling interrupts and auxiliary control circuit
An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt...
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