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7610426 |
System management mode code modifications to increase computer system security
Methods for processing more securely. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these...
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7581052 |
Approach for distributing multiple interrupts among multiple processors
A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors...
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7562173 |
Handling shared interrupts in bios under a virtualization technology environment
A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT)...
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7546406 |
Virtualization of a global interrupt queue
A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may...
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7502674 |
On-vehicle terminal system
In an on-vehicle terminal system operating a plurality of operating systems, control of peripheral devices connected to the on-vehicle terminal system can be continued even if one of the operating...
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7464211 |
Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment
A method for handling multiple system management interrupt (SMI) events in a multiprocessor system. The method comprises a first set of one or more processors in the multiprocessor system receiving...
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7464210 |
Data processing system having a data transfer unit for converting an integer into a floating-point number when tranferring data from a peripheral circuit to a memory
This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same...
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7454547 |
Data exchange between a runtime environment and a computer firmware in a multi-processor computing system
A method, system, apparatus, and computer-readable medium for exchanging data between an application program and a firmware in a computer system having multiple CPUs are provided. According to the...
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7447820 |
Retargeting of platform interrupts
Systems, methods, and apparatus to retarget platform interrupts in a reconfigurable system. Some embodiments include identifying each processor of a multiprocessor system capable of processing...
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7433985 |
Conditional and vectored system management interrupts
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode...
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7415561 |
Computer for dynamically determining interrupt delay
In a computer having a unit for outputting an interrupt request to a processor, a delay condition from occurrence of an interrupt event to issue of an interrupt request to the processor can be...
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7409483 |
Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers
Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that...
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7386646 |
System and method for interrupt distribution in a multithread processor
A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is...
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7363412 |
Interrupting a microprocessor after a data transmission is complete
A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with...
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7363411 |
Efficient system management synchronization and memory allocation
A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received,...
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7363409 |
Interrupt control system and method for reducing interrupt latency
An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event...
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7353312 |
Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device
A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU,...
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7350007 |
Time-interval-based system and method to determine if a device error rate equals or exceeds a threshold error rate
An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a...
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7350006 |
System and method of interrupt handling
A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor...
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7275122 |
Method and system for maintaining a desired service level for a processor receiving excessive interrupts
A method and system for maintaining a desired service level for a processor receiving excessive interrupts. The method includes the operation of defining an interrupt processing period during which...
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7263568 |
Interrupt system using event data structures
Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The...
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7263567 |
Method and apparatus for lowering the die temperature of a microprocessor and maintaining the temperature below the die burn out
According to one embodiment, a method is disclosed. The method includes determining whether the temperature of a central processing unit (CPU) exceeds a predetermined threshold. In addition, the...
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7222347 |
Method and apparatus for processing real-time events associated with a wireless communication protocol
A processor may perform real-time event processing of real-time events in a manner that enables a radio module equipped computer system to operate in accordance with a wireless communication...
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7222251 |
Microprocessor idle mode management system
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated...
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7206833 |
Platform independent alert detection and management
Platform independent alert detection and management. A software-based intermediary referred to herein as an alert proxy is used to transform binary, device-specific event or alert data into...
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7200701 |
System and method for processing system management interrupts in a multiple processor system
A system and method for processing system management interrupts in multiple processor systems is disclosed. In one embodiment, a method for processing a system management interrupt (SMI) in an...
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7197588 |
Interrupt scheme for an Input/Output device
Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a processor identifier and determines an event...
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7197587 |
Systems-events core for monitorings system events for a cellular computer system within a parent computer system, system-event manager for monitoring system events for more than one cellular computer system, and related system and method
A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell...
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7185125 |
Device for transferring data via write or read pointers between two asynchronous subsystems having a buffer memory and plurality of shadow registers
Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer...
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7181605 |
Deterministic shut down of memory devices in response to a system warm reset
A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of...
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7167893 |
Methods and systems for processing a plurality of errors
As part of handling a large amount of error information generated on a mainframe system associated, for example, with a telephone billing system, a utility software program allows a user to easily...
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7159058 |
State indicating information setting circuit and status bit setting circuit
A state indicating information setting circuit and a status bit setting circuit are responsive to detection of a predetermined state by a predetermined state detecting part for setting...
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7099963 |
Method and system for monitoring embedded disk controller components
A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a...
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7096296 |
Supercharge message exchanger
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store...
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7093036 |
Processor state aware interrupts from peripherals
A method, apparatus and computer product wherein interrupt thresholds are automatically adjusted based on the current state of the processor. The processor provides an output signal, possibly on...
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7086056 |
Processor unit for executing event processes in real time without causing process interference
A processor unit executes a failure detection program for a vehicle. The failure detection program includes a first failure detection process of a high priority level, a second failure detection...
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7076667 |
Storage device having secure test process
In a storage device for maintaining information when power is OFF and being capable of executing a test process based on test signals, a test terminal inputs the test signals and an instruction...
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7043729 |
Reducing interrupt latency while polling
Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system...
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7007119 |
System and method for supporting split transactions on a bus
System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node....
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7000051 |
Apparatus and method for virtualizing interrupts in a logically partitioned computer system
A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical...
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6973583 |
Information processing apparatus having an interrupt function
The present invention aims to reduce a waiting time of an information processing machine from reception of an interrupt request signal to an actual start of an interrupt process. The information...
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6968410 |
Multi-threaded processing of system management interrupts
An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected...
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6917997 |
Integrated circuit including interrupt controller with shared preamble execution and global-disable control bit
A interrupt controller includes specialized interfaces and controls for ARM7TDMI-type microcontroller cores. Such sends interrupt vectors and IRQ or FIQ interrupt requests to the processor...
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6889278 |
Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths
A system and technique provides fast acknowledgement and servicing of interrupt sources coupled to a high latency path of an intermediate node of a computer network. An external device coupled to...
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6851006 |
Interruption handler-operating system dialog for operating system handling of hardware interruptions
Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling...
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6820153 |
Interrupt processing and memory management method in an operation processing device and a device using the same
In operation processing devices based on Java (a registered trademark), each time a functional program is executed, in response to a command to access that function, a work area for the program...
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6745321 |
Method and apparatus for harvesting problematic code sections aggravating hardware design flaws in a microprocessor
A method and apparatus for harvesting problematic code sections that may cause a hang condition based on a hardware design flaw is presented. Monitoring is performed to detect a hang condition....
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6742089 |
Access controller and access method for controlling access from a CPU to a memory based on use states of plural access ports
An access controller comprising plural access ports in which information associated with access from a CPU is stored for each access, and a bank management unit for managing use states of the...
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6735690 |
Specifying different type generalized event and action pair in a processor
A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is...
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6718414 |
Function modification in a write-protected operating system
An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of the...
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