Matches 201 - 250 out of 295 < 1 2 3 4 5 6 >
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6000002 Protection circuit for program-controlled electrical equipment  
A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt...
5999993 Data transfer system having function of preventing error caused by suspension of data transfer to immediately service transfer interrupted request  
A data transfer system including a data transmission unit and a data reception unit, the data transmission unit including an arithmetic unit which, when accepting an interruption during data...
5991790 Generation and delivery of signals in a two-level, multithreaded system  
A system for properly delivering an signals in a computer system. A first module is called which waits for a signal to be generated. Upon a signal being generated, the first module is notified of...
5987560 Integrated programmable logic circuit for conditioning received input signals, detecting transitions of conditioned signals, and generating an associated interrupt respectively  
A flexible general input/output function utilizes a programmable logic circuit in conjunction with general purpose input/output pins. A programmable logic circuit receives the input signals from...
5987538 Apparatus for initiating generation of an inter-processor interrupt by a peripheral device not directly connected to any of the multi-processor local interrupt controllers  
Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer...
5987559 Data processor with protected non-maskable interrupt  
An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority...
5968172 Hardware and software triggered programmable reset circuitry for serial communication device  
Hardware and software triggered programmable reset circuitry for a serial communication device. The invention has particular use in conjunction with an IEEE 1394 standard serial communication...
5961585 Real time architecture for computer system  
A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To...
5944809 Method and apparatus for distributing interrupts in a symmetric multiprocessor system  
A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable...
5944816 Microprocessor configured to execute multiple threads including interrupt service routines  
A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the...
5941976 Interrupt request deassertion interlock mechanism  
An interrupt circuit on a first integrated circuit receives a plurality of interrupt request signals, at least one of which is provided over a bus. A interrupt synchronization control circuit...
5933622 Method for efficient handling of asynchronous events in a dynamic translation system  
A method for operating a computer to allow the running of a source program written for a first computer on a second computer. The second computer is assumed to include a branch taken trap. The...
5925115 Method and system for extending interrupt sources and implementing hardware based and software based prioritization of interrupts for an embedded processor  
The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt...
5923887 Interrupt request that defines resource usage  
An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a...
5918056 Segmentation suspend mode for real-time interrupt support  
A device and method that suspends segmentation addressing and prevents the modification of segmentation information (the segment registers and segment descriptors). By suspending segmentation...
5913045 Programmable PCI interrupt routing mechanism  
An element of a multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge (P2P). The invention is part of a design that consolidates a high performance...
5905898 Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority  
A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage...
5901309 Method for improved interrupt handling within a microprocessor  
A method and apparatus for processing interrupts received by a processor during the processing of an instruction set by a processing pipeline is disclosed. Initially, an interrupt associated with...
5894578 System and method for using random access memory in a programmable interrupt controller  
A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central...
5894583 Variable timeout method for improving missing-interrupt-handler operations in an environment having I/O devices shared by one or more systems  
Missing interrupt handler (MIH) software features for supporting a variable MIH timeout for I/O requests issued by an operating system (OS). The MIH timeout is varied to prevent a false indication...
5892956 Serial bus for transmitting interrupt information in a multiprocessing system  
A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line...
5889973 Method and apparatus for selectively controlling interrupt latency in a data processing system  
Method and apparatus for selectively controlling interrupt latency in a data processing system (10). In one embodiment, the present invention uses an interrupt control register bit field (50) to...
5881294 System for transforming PCI level interrupts  
A system for transforming computer system interrupts from state based interrupts to event based interrupts. The system of the present invention includes an interrupt acknowledge detection circuit...
5875341 Method for managing interrupt signals in a real-time computer system  
A method for the operation of a computer system controlled by a real-time operating system, which computer system processes interrupt signals. Upon the occurrence of an interrupt signal, the...
5864346 Picture display unit and image display system  
When a game is started, the game execution time is counted by a counter and a determination is made as to whether or not the execution time coincides with a timer value which is set before the game...
5864843 Method and apparatus for extending a database management system to operate with diverse object servers  
A method and apparatus for extending a database management system to operate with diverse object servers. The apparatus comprises a federated coordinator for accepting client commands and...
5862340 Method operating in each node of a computer system providing and utilizing special records for collective communication commands to increase work efficiency at each node  
A testing apparatus designed to check the completion of a command issued earlier in a multiprocessing system having a plurality of nodes. During an initialization phase, each command has been...
5862389 Method and apparatus for selectively invoking a particular interrupt service routine for a particular interrupt request  
A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per...
5857090 Input/output subsystem having an integrated advanced programmable interrupt controller for use in a personal computer  
A computer system is described having one or more host processors, a host chipset and a input/output (I/O) subsystem. The host processors are connected to the host chipset by a host bus. The host...
5850555 System and method for validating interrupts before presentation to a CPU  
A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity...
5845131 Multiprocessor system employing an improved self-coded distributed interrupt arbitration technique  
A multiprocessor system has a shared bus and a plurality of processor modules, wherein the shared bus includes an interrupt bus and each of the processor module contains an interrupt controller....
5842026 Interrupt transfer management process and system for a multi-processor environment  
An interrupt mechanism handles an interrupt transaction between a source processor and a target processor on separate nodes in a multi-processor system. The nodes are connected to a network through...
5832279 Advanced programmable interrupt controller (APIC) with high speed serial data bus  
A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for prioritizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts...
5828890 System for interrupting program operation when an out-of-range value is encountered to correct a data value  
System for suspending operation of a program after detecting that an instruction is executing with an operand assuming an out-of-range value such as a year value out of the range of the program....
5828891 Multilevel interrupt device  
The invention relates to multilevel interrupt device (10) using a common microprocessor interrupt signal (101) to process interrupt signals (INT1, . . . , INTN) received from N peripheral chips....
5819095 Method and apparatus for allowing an interrupt controller on an adapter to control a computer system  
A method and apparatus of making a computer system using the peripheral component interconnect (PCI) bus architecture compatible with an Apple computer system are provided. In a preferred...
5799195 Structure and method for detecting occurrence of external events using semaphores  
In a cached computer environment, an additional mechanism for communicating to a processor the occurrence of an external hardware event is provided through semaphores in the main memory. In one...
5796996 Processor apparatus and its control method for controlling a processor having a CPU for executing an instruction according to a control program  
In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer,...
5797037 Interrupt request control logic reducing the number of interrupts required for I/O data transfer  
A DMA data transfer system is provided with an interrupt request controller that has pass through logic, data limit logic, stale data logic and error detecting logic to monitor for predetermined...
5797021 Information processing apparatus for emulation  
An INTC and a CPU are interconnected via a bus. A first line through which an interrupt request signal is transferred to the CPU from the INTC, and a second line through which an interrupt...
5787290 Adapter with an onboard interrupt controller for controlling a computer system  
A CHRP compliant Apple adapter is provided. The adapter comprises an onboard interrupt controller to control a peripheral component interconnect (PCI) based computer system. The adapter also...
5778236 Multiprocessing interrupt controller on I/O bus  
A multiprocessing computer system which includes an interrupt controller coupled to an expansion bus. The programmable interrupt controller has multiple storage locations at the same address for...
5768617 Intelligent hardware for automatically reading and writing multiple sectors of data between a computer bus and a disk drive  
The transfer of multiple sectors of data between a hard disk drive and a computer data bus of a host computer is controlled by hardware within a computer bus interface circuit of a storage...
5765000 Dynamic user interrupt scheme in a programmable logic controller  
The scan cycle in a programmable logic controller is constructed so as to allow the PLC users program to execute an instruction to assign a user program section to which the PLC system is to...
5761482 Emulation apparatus  
An access condition coincidence detecting circuit detects that an address stored in an access condition storing register 44 is outputted to an address bus 29. When a counter 46 counts a certain...
5758169 Protocol for interrupt bus arbitration in a multi-processor system  
A multi-processor system includes an interrupt bus used for arbitrating among eligible processors to determine which processor is to service of an interrupt request. The interrupt bus comprises...
5752083 Method for receiving a first SCSI command, subsequent receiving second SCSI command and starting data transfer, reconnecting and performing data transfer for first SCSI command  
A hard disk controller integrated circuit of a SCSI target-device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution...
5748970 Interrupt control device for processing interrupt request signals that are greater than interrupt level signals  
An interrupt control device of an embedded microcomputer including I/O devices and a processor core comprising: a program storage unit for storing interrupt processing programs, each corresponding...
5734911 Method of linking peripheral devices all of which use the same IRQ to a single interrupt procedure  
A method of linking peripheral devices to a single interrupt procedure in a computer is comprised of storing in an interrupt vector table of a BIOS ROM, a first pointer to an interrupt service...
5724527 Fault-tolerant boot strap mechanism for a multiprocessor system  
A multiprocessor computing system includes a serial bus and implements a boot protocol in which each processor compares a vector field of a boot message issued on the serial bus by a first...
Matches 201 - 250 out of 295 < 1 2 3 4 5 6 >