Matches 151 - 200 out of 295 < 1 2 3 4 5 6 >
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6279108 Programmable microcontroller architecture for disk drive system  
The software system architecture supports a rotating media in the storage and retrieval of data, where the rotating media stores in data tracks of multiple sectors, through the use of a...
6279067 Method and apparatus for detecting interrupt requests in video graphics and other systems  
A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple...
6272585 Multiple interrupt handling method and apparatus  
A method and an apparatus for handling interrupt requests generated by a plurality of interrupt sources (2A, 2N) for a processor. The method includes steps of scanning interrupt registering means...
6263397 Mechanism for delivering interrupt messages  
An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination...
6263396 Programmable interrupt controller with interrupt set/reset register and dynamically alterable interrupt mask for a single interrupt processor  
A programmable interrupt controller (510) for a single interrupt architecture processor (518) includes a plurality of interrupt sources (502) each operable to generate an interrupt. A dynamically...
6253275 Interrupt gating method for PCI bridges  
A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device...
6247091 Method and system for communicating interrupts between nodes of a multinode computer system  
Each node of multinode computer system includes an interrupt controller, a pair of send and receive queues, and a state machine for communicating interrupts between nodes. The communication among...
6237058 Interrupt load distribution system for shared bus type multiprocessor system and interrupt load distribution method  
An interrupt load distribution system for a shared bus type multiprocessor system includes a processor statistical information table for storing processor statistical information consisting of...
6223246 Computer system having an interrupt handler  
Referred to is a flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag. As a result thereof, it is determined whether...
6219727 Apparatus and method for computer host system and adaptor interrupt reduction including clustered command completion  
The number of interrupts are controlled by delaying communication of the interrupt to the host computer or processor according to predetermined rules. This reduces the processing overhead and...
6212593 Method and apparatus for generating interrupts on a buffer by buffer basis in buffer descriptor ring direct memory access system  
A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an...
6212594 Timer with fixed and programmable interrupt periods  
A method for causing two programmable interrupts to take place is described herein, using a counter having an output having an adjustable period, a first register which controls the length of the...
6205507 Memory coherency in a processor-to-bus cycle in a multi-processor system  
In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an...
6202174 Method for identifying and correcting errors in a central processing unit  
A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the...
6195715 Interrupt control for multiple programs communicating with a common interrupt by associating programs to GP registers, defining interrupt register, polling GP registers, and invoking callback routine associated with defined interrupt register  
A method and an system for communication between components of a computer system, such a plurality of computer soft-ware applications stored in a memory, that features uniquely associating each of...
6195725 Dynamically varying interrupt bundle size  
A system generates interrupts in response to events and dynamically accommodates for changing rates of event generation. A number of events may be bundled together to generate one or more...
6189049 Method for operating processor with internal register for peripheral status  
One embodiment of the present invention provides a method that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the...
6185652 Interrupt mechanism on NorthBay  
An interrupt tracking mechanism includes a CPU that handles interrupts generated by an interrupt generator, a storage element accessible to the CPU, an interrupt counter implemented in hardware and...
6182238 Fault tolerant task dispatching  
A fault tolerant task dispatching technique schedules a plurality of tasks, monitors the progress of each task on a periodic basis, detects when a task has failed, and initializes a failed task in...
6167480 Information packet reception indicator for reducing the utilization of a host system processor unit  
A reception indicator is within a network peripheral that receives information packets for a host system from a communications network. The reception indicator of the present invention allows the...
6167512 Dynamic creation of ACPI APIC tables using MP specification  
A method and system for dynamic creation of APIC tables under the ACPI specification using existing APIC tables under the MP specification in a multi-processor computer. The method of the present...
6148361 Interrupt architecture for a non-uniform memory access (NUMA) data processing system  
A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The...
6141700 Data processor which accesses a second memory while responding to an interrupt request during programming and erasing mode of first erasable and programmable non-volatile memory  
To obtain a correct vector address even if an interrupt occurs during erasing or programing of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus...
6128691 Apparatus and method for transporting interrupts from secondary PCI busses to a compatibility PCI bus  
During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication...
6115780 Interrupt steering circuit for PCI bus  
In an interrupt steering circuit for a computer system having a PCI bus connected to four expansion slots, a controller includes a non-volatile memory previously storing a selection information of...
6115776 Network and adaptor with time-based and packet number based interrupt combinations  
A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates...
6115779 Interrupt management system having batch mechanism for handling interrupt events  
An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request...
6115756 Electro-optically connected multiprocessor and multiring configuration for dynamically allocating time  
A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and the modules are coupled to one or...
6112274 Method and apparatus for processing more than one interrupts without reinitializing the interrupt handler program  
A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage...
6108744 Software interrupt mechanism  
An interrupt mechanism for an operating system is portable to different data processing hardware. The interrupt mechanism includes a software interrupt management component which manages at least...
6105102 Mechanism for minimizing overhead usage of a host system by polling for subsequent interrupts after service of a prior interrupt  
An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines,...
6105081 UART character matching used for address matching on a register-by-register basis  
An asynchronous serial port is provided in a microcontroller that includes an address matching function that includes character matching functions such that incoming data is compared to match...
6101571 Circuit configuration for generating an interrupt signal for a microprocessor  
A circuit configuration for generating an interrupt signal for a microprocessor includes a multiplicity of signal generating circuits that are connected to one another via a logic combination...
6092143 Mechanism for synchronizing service of interrupts by a plurality of data processors  
An apparatus and method ensure that only one data processor, within a multiprocessor system, performs operations associated with an interrupt register having information corresponding to a...
6085278 Communications interface adapter for a computer system including posting of system interrupt status  
To facilitate access of interrupt status information, interrupt posting status. POST - - STAT registers are readable by a host driver routine to quickly supply information relating to a functional...
6085325 Method and apparatus for supporting power conservation operation modes  
An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal...
6081867 Software configurable technique for prioritizing interrupts in a microprocessor-based system  
A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an...
6070221 Interrupt controller  
An interrupt controller comprises a plurality of interrupt handling elements that are given different identification numbers for identification to which priorities are assigned. A first priority...
6070218 Interrupt capture and hold mechanism  
A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an...
6065122 Smart battery power management in a computer system  
A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management...
6065089 Method and apparatus for coalescing I/O interrupts that efficiently balances performance and latency  
A method and apparatus for generating an interrupt signal. A counter value is decremented each time a task is completed by a slave processor. The counter value is incremented each time a task is...
6065073 Auto-polling unit for interrupt generation in a network interface device  
A system and method for auto-polling a status register within a physical layer (PHY) interface to a local area network (LAN). The system includes a host CPU which needs to detect and service...
6047351 Jitter free instruction execution  
A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program...
6044414 System for preventing a DMA controller from evaluating its DRQ input once a DMA operation has started until the DRQ input has been updated  
A computer system includes first and second integrated circuits. A direct memory access (DMA) controller circuit on the first integrated circuit receives a direct memory access request (DRQ) input...
6032213 PC core logic chipset comprising a serial register access bus  
A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first...
6029223 Advanced programmable interrupt controller  
A computer system having an advanced programmable interrupt controller (APIC) is described in which an I/O APIC module is included in core logic circuitry coupled between a processor bus and a...
6029153 Method and system for analyzing and handling the customer files of a financial institution  
A system and method for identifying and communicating the availability of additional products to at least one customer of a financial institution is disclosed. A processor analyses data about the...
6021458 Method and apparatus for handling multiple level-triggered and edge-triggered interrupts  
Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector...
6021457 Method and an apparatus for minimizing perturbation while monitoring parallel applications  
A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes...
6016548 Apparatus for controlling duty ratio of power saving of CPU  
A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a...
Matches 151 - 200 out of 295 < 1 2 3 4 5 6 >