Matches 101 - 150 out of 295 < 1 2 3 4 5 6 >
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6718413 Contention-based methods for generating reduced number of interrupts  
Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from...
6704823 Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing  
A method and an apparatus is present for dynamically allocating a set of output interrupt lines at a host adapter to a set of input interrupt lines for card slots controlled by the host adapter. If...
6684281 Fast delivery of interrupt message over network  
A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt...
6665761 Method and apparatus for routing interrupts in a clustered multiprocessor system  
A method and apparatus for increasing the routing bandwidth of interrupts between cluster manager devices in a clustered multiprocessor system is disclosed. This is accomplished by providing...
6658515 Background execution of universal serial bus transactions  
A method, computer program product and computer system that features intermittently entering the system management mode of a processor to commence and terminate I/O activity between external...
6640274 Method and apparatus for reducing the disk drive data transfer interrupt service latency penalty  
A method and apparatus for reducing the disk drive data transfer interrupt service latency penalty is described. The method comprises beginning a data transfer between a disk drive and a host...
6636916 Assigning PCI device interrupts in a computer system  
A method and apparatus for assigning interrupts to devices on a PCI bus in a computer system in which a plurality of address lines are channeled through a multiplexer to a PCI device on the PCI...
6631434 Dynamic early indication system for a computer  
A dynamic early indication system for a computer includes a processor subsystem logic that performs a subsystem function, an early indicator, indication logic, and a driver that is executed by the...
6618780 Method and apparatus for controlling interrupt priority resolution  
A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a...
6618779 Method and apparatus for chaining interrupt service routines  
A method of chaining interrupt service routines comprises creating a chain handler module and replacing an instruction in an existing interrupt service routine with a branch directed to the chain...
6615305 Interrupt pacing in data transfer unit  
An apparatus and method for controlling the number of interrupts a data transfer unit generates to a CPU is disclosed. A pacing unit is used to register attempted data transfers (events) from a...
6615342 Method and apparatus for object-oriented interrupt system  
An object-oriented interrupt processing system in a computer system creates a system database including a device namespace containing an entry for each device in the computer system and an...
6615288 Generating system management interrupt in response to usb controller signal and processing interrupt routine in upper most level of system memory  
Systems and methods for enabling computer system devices and components are disclosed. A method for use in a computer system having a processor includes receiving an input from a device coupled to...
6606677 High speed interrupt controller  
A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its...
6606676 Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
6601131 Flash memory access control via clock and interrupt management  
A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a...
6601122 Exceptions and interrupts with dynamic priority and vector routing  
A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request...
6598105 Interrupt arbiter for a computing system  
An interrupt arbiter for a computer is described. The arbiter allocates interrupt resources to a plurality of devices within a computer such as a modem, keyboard, video controller, serial port,...
6584511 Loop initialization procedure exception handling for fibre channel transmissions  
A fiber optic channel loop provides a transmission path between a computer platform and a multiple number of peripheral devices. When any change occurs in the number of connected peripheral devices...
6581119 Interrupt controller and a microcomputer incorporating this controller  
To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers...
6574693 Method and apparatus for gating interrupts in a computing system  
A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event...
6574702 Method and apparatus for determining an exact match in a content addressable memory device  
A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the...
6532401 Methods for automatically verifying the performance of a virtual robot  
In an automated interface program designed to interact and communicate with users, said program executing actions when a category among a predefined set of categories is activated, a method is...
6529975 Method and apparatus for addressing and controlling exspansion devices through an AC-link and a codec  
In one embodiment, a single designated register in a codec is utilized by a controller to address and control a large number of expansion registers belonging to various expansion devices. The...
6502213 System, method, and article of manufacture for a polymorphic exception handler in environment services patterns  
A system, method and article of manufacture are provided for minimizing the amount of changes that need to be made to exception handling logic when new exceptions are added. Exceptions are...
6499078 Interrupt handler with prioritized interrupt vector generator  
A hardware-implemented interrupt handler external to a processor handles interrupts destined for the processor. The interrupt handler has a programmable prioritized interrupt array with...
6487606 System and method for delivering messages through a totem communications system  
An improvement is disclosed for a Totem system having a network and a plurality of host processors connectable to the network, each of which host processors includes a CPU and is configured for...
6467007 Processor reset generated via memory access interrupt  
An apparatus, program product, and method utilize a memory access interrupt to effect a reset of a processor in a multi-processor environment. Specifically, a source processor is permitted to...
6466998 Interrupt routing mechanism for routing interrupts from peripheral bus to interrupt controller  
An interrupt routing mechanism implemented in a host chipset to eliminate the need for the general purpose I/O pins, special software and external logic devices to steer particular interrupts from...
6457082 Break event generation during transitions between modes of operation in a computer system  
A break event in a computer system that can operate in one of a plurality of modes, such as a high performance mode and a low power mode is initiated only be logic that that detects when the...
6434633 Method and apparatus for facilitating AC-link communications between a controller and a slow peripheral of a codec  
A method and apparatus for facilitating AC-link communications between a controller and a slow peripheral of a codec is disclosed. In one embodiment, the GPIO_INT bit (i.e. bit 0 in slot 12 in...
6421754 System management mode circuits, systems and methods  
An electronic system ( 100 ) includes a first integrated circuit (IC) ( 112 ) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ 3-5 ), and a logic circuit...
6418489 Direct memory access controller and method therefor  
Direct memory access controller (DMA) ( 2 ) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second...
6412062 Injection control mechanism for external events  
The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified....
6412081 System and method for providing a trap and patch function to low power, cost conscious, and space constrained applications  
A system and method for providing a software trap and patch function to low power, cost conscious, and space constrained applications. When a programming error in a first memory is discovered, a...
6405268 Dynamic block processing in a host signal processing modem  
A host signal processing (HSP) modem or transceiver includes a transmit buffer and a receive buffer. The transmit buffer stores multiple blocks of information representing a transmit signal, and...
6401154 Flexible architecture for an embedded interrupt controller  
A programmable interrupt controller arrangement is provided including a multiple number of selectably enabled programmable interrupt controllers along with a multi-channel switch matrix. A scalable...
6401153 Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals  
In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes...
6401155 Interrupt/software-controlled thread processing  
Rapid thread processing is achieved by transferring complete thread contexts between a memory and a context register set. Each thread context is read from a respective memory location in response...
6401156 Flexible PC/AT-compatible microcontroller  
A microcontroller for PC/AT-compatible or non-PC/AT compatible embedded environments is disclosed. The microcontroller includes a general purpose bus which may emulate an ISA bus in a...
6397284 Apparatus and method for handling peripheral device interrupts  
A computer system having a PCI expansion connector and further including: an operating system operable to detect a PCI-to-PCMCIA bridge on the PCI expansion connector and in response thereto to...
6385683 Methods and apparatus for raid hardware sequencing to achieve a higher performance raid architecture  
The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller ( 10 ) includes a main processor ( 12 ), a memory ( 14 ), a device...
6374321 Mechanisms for converting address and data signals to interrupt message signals  
In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge...
6356969 Methods and apparatus for using interrupt score boarding with intelligent peripheral device  
In one embodiment, the present invention provides a storage system controller ( 10 ) having a main processor ( 12 ), a memory ( 14 ) and a device interface ( 18 ) adapted to interface with a...
6339832 Exception response table in environment services patterns  
A system, method and article of manufacture are provided for recording exception handling requirements for maintaining a consistent error handling approach. An exception response table is provided...
6338098 Processor with internal register for peripheral status  
One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a...
6298410 Apparatus and method for initiating hardware priority management by software controlled register access  
An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to...
6298409 System for data and interrupt posting for computer devices  
A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction...
6292862 Bridge module  
The bridge module is connected between at least two bus systems and is suitable for serial data transfer of binary data from one of the bus systems to the other one of the bus systems. A single...
6286346 Interruptable multiply and/or divide operations for use with an interrupt in a medical device processor  
A method and apparatus including conditional add and conditional add/subtract instructions are provided for use in the instruction set of a medical device instruction processor. More specifically,...
Matches 101 - 150 out of 295 < 1 2 3 4 5 6 >