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7617346 Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency  
Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding...
7617345 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts  
A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for...
7613860 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts  
A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for...
7607133 Interrupt processing control  
A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24 . The interrupt controller is responsive to save state data when interrupt processing is...
7552371 Method and system for automatically diagnosing disability of computer peripheral devices  
A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral...
7552261 Configurable prioritization of core generated interrupts  
A method and apparatus for generating an interrupt vector associated with either core (internal) generated or off-core (external) generated interrupts is provided. The apparatus includes a number...
7549039 Generating an interrupt in a system having plural partitions that share a resource  
A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is...
7533207 Optimized interrupt delivery in a virtualized environment  
Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit...
7523240 Interrupt controller and interrupt control method  
An interrupt controller superior in maintenance performance and expandability. An interrupt controller 10 comprises a queue circuit 11 that holds channel numbers corresponding to interrupt...
7516252 Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment  
Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and...
7484024 Apparatus and method for interrupt source signal allocation  
An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control...
7478186 Interrupt coalescer for DMA channel  
A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied...
7472214 Real-time embedded simple monitor method and computer product  
A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the...
7444450 Method and system for detecting excessive interrupt processing for a processor  
A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of...
7433985 Conditional and vectored system management interrupts  
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode...
7426728 Reducing latency, when accessing task priority levels  
One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is...
7415557 Methods and system for providing low latency and scalable interrupt collection  
A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an...
7379418 Method for ensuring system serialization (quiesce) in a multi-processor environment  
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
7370193 Computing system being able to quickly switch between an internal and an external networks and a method thereof  
The invention discloses a computing system such as a computer, a Personal Digital Assistant, or a mobile phone, being connected both to an internal network and an external network and being able to...
7369256 Interruption of job in information processing apparatus by means of acquisition and release of resources  
An information processing apparatus, which attends to inputting and outputting of image data, and processes the image data by performing a job that uses a resource, includes a time-division...
7356359 Device detection in a mobile communication terminal  
A method for determining connection of an external device to a mobile communication terminal is provided. The method comprises detecting connection of an external device to a mobile communication...
7350006 System and method of interrupt handling  
A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor...
7350005 Handling interrupts in a system having multiple data processing units  
An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request...
7340547 Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system  
A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether...
7328295 Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources  
An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an...
7328294 Methods and apparatus for distributing interrupts  
The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and...
7318113 System and method communication system for reading or writing data to register between external card connection device and host device  
This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card ( 1 )...
7316017 System and method for allocatiing communications to processors and rescheduling processes in a multiprocessor system  
In a multiprocessor system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a...
7281073 Method for controlling interrupts and auxiliary control circuit  
An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt...
7240170 High/low priority memory  
Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In...
7222251 Microprocessor idle mode management system  
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated...
7222204 Testing the interrupt priority levels in a microprocessor  
A method of testing the priority levels of the interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when...
7213137 Allocation of processor bandwidth between main program and interrupt service instruction based on interrupt priority and retiring micro-ops to cache  
The method and apparatus feature detecting an interrupt service request; storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request; and...
7209994 Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests  
In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is...
7209993 Apparatus and method for interrupt control  
An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system...
7165134 System for selectively generating real-time interrupts and selectively processing associated data when it has higher priority than currently executing non-real-time operation  
A method is disclosed. The method includes receiving real-time data at a personal computer implementing a general purpose operating system, generating a real-time event at the personal computer and...
7162558 Interrupt signal processing circuit for sending interrupt requests to a computer system  
A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources,...
7159057 Evaluation chip  
An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20 - 1 to 2 - 4 perform a logical operation on...
7149831 Batch processing of interrupts  
A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working...
7143197 Method and system for monitoring a telecommunications signal transmission link  
A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to...
7133951 Alternate set of registers to service critical interrupts and operating system traps  
A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task...
7120718 Method for generating interrupt commands in a microprocessor system and relative priority interrupt controller  
A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored...
7111089 Programmable scheduler for digital signal processor  
A digital signal processor operates in conjunction with a scheduler hardware module and a scheduler software module in executing a highest priority runnable event among a plurality of events. The...
7086056 Processor unit for executing event processes in real time without causing process interference  
A processor unit executes a failure detection program for a vehicle. The failure detection program includes a first failure detection process of a high priority level, a second failure detection...
7080188 Method and system for embedded disk controllers  
A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a...
7080178 Interrupt pre-emption and ordering within a data processing system  
A data processing system nested interrupt controller 24 responsive to priority level values 28, 30 associated with respective interrupt handling programs to control the execution of those...
7054972 Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system  
An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO...
7051128 System and method for data bus communication system between external card connection device and host device  
This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card ( 1 )...
7043729 Reducing interrupt latency while polling  
Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system...
7043584 Interrupt prioritization in a digital disk apparatus  
In an digital video disk player the timely acquisition of specific data types is particularly important during trick mode operation. During trick modes a controller can provide enhanced control...
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