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7631114 |
Serial communication device
The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the...
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7610426 |
System management mode code modifications to increase computer system security
Methods for processing more securely. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these...
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7600100 |
Instruction encoding for system register bit set and clear
An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the...
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7590982 |
System and method for virtualizing processor and interrupt priorities
Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum...
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7587544 |
Extending secure digital input output capability on a controller bus
Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.
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7584310 |
Signal processing device
A signal processing device includes a start time obtaining part that obtains a start time when a predetermined process is started in response to an interrupt request associated with a valid edge of...
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7552371 |
Method and system for automatically diagnosing disability of computer peripheral devices
A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral...
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7549082 |
Method and system of bringing processors to the same computational point
A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a...
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7549005 |
System and method for managing interrupts
Method and system for managing interrupts originating from multiple sources is provided. The method includes assigning interrupt sources to a group; notifying an adapter of interrupt groups;...
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7546446 |
Selective interrupt suppression
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation...
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7543095 |
Managing input/output interruptions in non-dedicated interruption hardware environments
Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment...
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7526592 |
Interrupt control system and storage control system using the same
An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system...
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7503049 |
Information processing apparatus operable to switch operating systems
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
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7500039 |
Method for communicating with a processor event facility
A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The...
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7487503 |
Scheduling threads in a multiprocessor computer
Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a...
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7478185 |
Directly initiating by external adapters the setting of interruption initiatives
The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a...
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7426728 |
Reducing latency, when accessing task priority levels
One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is...
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7423565 |
Apparatus and method for comparison of a plurality of analog signals with selected signals
In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a...
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7421521 |
System, method and device for real time control of processor
A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may,...
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7398343 |
Interrupt processing system
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding...
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7386647 |
System and method for processing an interrupt in a processor supporting multithread execution
A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to...
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7380063 |
Cache flushing
Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second...
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7363412 |
Interrupting a microprocessor after a data transmission is complete
A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with...
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7356817 |
Real-time scheduling of virtual machines
A method for scheduling a plurality of virtual machines includes: determining a resource requirement (X i ) for each virtual machine (VM); determining an interrupt period (Y i ) for each VM; and...
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7353370 |
Method and apparatus for processing an event occurrence within a multithreaded processor
A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor...
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7353312 |
Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device
A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU,...
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7350005 |
Handling interrupts in a system having multiple data processing units
An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request...
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7340547 |
Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system
A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether...
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7328295 |
Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources
An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an...
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7325084 |
Messages signaling interrupt (MSI) processing system
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding...
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7320044 |
System, method, and computer program product for interrupt scheduling in processing communication
Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving...
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7315911 |
Method for efficient inter-processor communication in an active-active RAID system using PCI-express links
A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a...
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7308518 |
Interrupt controlling circuit
Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling module 105 is provided for each interrupt. An interrupt...
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7299379 |
Maintaining cache integrity by recording write addresses in a log
An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache...
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7296257 |
Techniques for exception handling by rewriting dispatch table elements
A technique for implementing a data processor to determine if an exception has been thrown. Specifically, the technique may be used in an interpretive environment where a table known as a bytecode...
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7281073 |
Method for controlling interrupts and auxiliary control circuit
An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt...
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7240170 |
High/low priority memory
Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In...
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7240137 |
System and method for message delivery across a plurality of processors
A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue...
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7222251 |
Microprocessor idle mode management system
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated...
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7209994 |
Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests
In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is...
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7206884 |
Interrupt priority control within a nested interrupt system
A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly...
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7197587 |
Systems-events core for monitorings system events for a cellular computer system within a parent computer system, system-event manager for monitoring system events for more than one cellular computer system, and related system and method
A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell...
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7191443 |
Digital device, task management method and program therefor
A task management method is provided for preventing a task that can cause a failure in a system from being aborted during a manipulation of the task. A program execution means transmits information...
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7191275 |
System and method for the management of hardware triggered hotplug operations of input/output cards
A method is provided of managing hardware triggered hotplug operations of one or more input/output (I/O) cards of a computer system. The method comprises receiving hardware triggers, each of which...
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7188203 |
Method and apparatus for dynamic suppression of spurious interrupts
An apparatus and method for dynamic suppression of spurious interrupts in a computer system. More specifically, there is provided a method that comprises providing a look-up table comprising source...
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7174554 |
Tools and methods for discovering race condition errors
Tools and methods are described herein for discovering race condition errors in a software program. The errors are discovered by deliberately causing a processor executing the test program to...
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7165134 |
System for selectively generating real-time interrupts and selectively processing associated data when it has higher priority than currently executing non-real-time operation
A method is disclosed. The method includes receiving real-time data at a personal computer implementing a general purpose operating system, generating a real-time event at the personal computer and...
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7162559 |
System for controlling interrupts between input/output devices and central processing units
An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at...
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7143274 |
Setting breakpoint for postponed interrupt processing in subsequent area while executing interrupt-exclusive task area to avoid slow down
An interrupt controlling method is provided that is capable of executing an interrupt process while avoiding slowing-down in execution speed of a task process. When an interrupt request occurs...
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7143197 |
Method and system for monitoring a telecommunications signal transmission link
A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to...
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