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7603504 Reducing core wake-up latency in a computer system  
A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect...
7590877 Computer system having multi-operation system and method for changing operating system in computer system  
Embodiments of a computer system and methods for changing operating systems (OSs) can perform a task switching into a different OS without checking a system reset or power off of the system. A...
7587717 Dynamic master/slave configuration for multiple expansion modules  
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
7587510 System and method for transferring data between a user space and a kernel space in a server associated with a distributed network environment  
A system ( 150 ) and method provide for the transfer of at least one packet ( 194 ) comprising data between a user space ( 152 ) and a kernel space ( 154 ) associated with a server ( 156 ) that is...
7562173 Handling shared interrupts in bios under a virtualization technology environment  
A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT)...
7558897 Method for adopting an orphan I/O port in a redundant storage controller  
A method for adopting an orphaned I/O port of a storage controller is disclosed. The storage controller has first and second redundant field-replaceable units (FRU) for processing I/O requests and...
7555086 Plural circuit selection using role reversing control inputs  
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
7552371 Method and system for automatically diagnosing disability of computer peripheral devices  
A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral...
7543095 Managing input/output interruptions in non-dedicated interruption hardware environments  
Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment...
7533201 Queue management mechanism in network processor wherein packets stored at memory device corresponds to addresses stored in plurity of queues within queue management  
According to one embodiment, a method is disclosed. The method includes selecting a first of a plurality of programmable interrupt enable registers, a controller determining for the first register...
7506091 Interrupt controller utilising programmable priority values  
An interrupt controller 2 is provided with priority registers 6 storing priority values P 0 -P 9 used to determine prioritisation between received interrupt signals I 0 -I 9 . A priority value...
7502674 On-vehicle terminal system  
In an on-vehicle terminal system operating a plurality of operating systems, control of peripheral devices connected to the on-vehicle terminal system can be continued even if one of the operating...
7493535 JTAG circuit transferring data between devices on TCK terminals  
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK...
7433986 Minimizing ISR latency and overhead  
The capability to handle the 100 μs RPR interrupt and similar interrupts is provided by servicing selected interrupts outside of the operating system. This drastically reduces the latency and...
7433985 Conditional and vectored system management interrupts  
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode...
7424563 Two-level interrupt service routine  
A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt...
7415559 Data processing systems and method for processing work items in such systems  
Described is a method for processing work items in a data processing system. An interrupt is generated in response to receipt of a work item on a queue and the generated interrupt is serviced to...
7415087 Circuits with state circuitry having cross connected control inputs  
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
7409483 Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers  
Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that...
7383587 Exception handling control in a secure processing system  
A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain,...
7379418 Method for ensuring system serialization (quiesce) in a multi-processor environment  
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
7373446 Method and system for dynamically patching an operating system's interrupt mechanism  
In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software....
7363411 Efficient system management synchronization and memory allocation  
A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received,...
7350007 Time-interval-based system and method to determine if a device error rate equals or exceeds a threshold error rate  
An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a...
7350006 System and method of interrupt handling  
A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor...
7330926 Interruption control system  
An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status...
7325083 Delivering data processing requests to a suspended operating system  
In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second...
7320044 System, method, and computer program product for interrupt scheduling in processing communication  
Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving...
7315911 Method for efficient inter-processor communication in an active-active RAID system using PCI-express links  
A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a...
7302512 Interrupt steering in computing devices to effectuate peer-to-peer communications between device controllers and coprocessors  
A computer device, an input/output ("I/O") communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between...
7281073 Method for controlling interrupts and auxiliary control circuit  
An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt...
7254726 System and method for managing system events by creating virtual events in an information handling system  
In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the...
7222251 Microprocessor idle mode management system  
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated...
7222204 Testing the interrupt priority levels in a microprocessor  
A method of testing the priority levels of the interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when...
7209993 Apparatus and method for interrupt control  
An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system...
7206833 Platform independent alert detection and management  
Platform independent alert detection and management. A software-based intermediary referred to herein as an alert proxy is used to transform binary, device-specific event or alert data into...
7197586 Method and system for recording events of an interrupt using pre-interrupt handler and post-interrupt handler  
A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’...
7194623 Data event logging in computing platform  
There is disclosed a computer entity having a trusted component which compiles an event log for events occurring on a computer platform. The event log contains event data of types which are...
7180971 Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals  
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
7177963 System and method for low-overhead monitoring of transmit queue empty status  
A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of...
7171501 System and method for asynchronous transfer of control  
An invention is provided for a synchronous transfer of control. An asynchronous interrupt exception is received, and in response, the value of a reference counter is determined. The value of the...
7152125 Dynamic master/slave configuration for multiple expansion modules  
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
7143197 Method and system for monitoring a telecommunications signal transmission link  
A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to...
7133951 Alternate set of registers to service critical interrupts and operating system traps  
A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task...
7131114 Debugger breakpoint management in a multicore DSP device having shared program memory  
A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of...
7130951 Method for selectively disabling interrupts on a secure execution mode-capable processor  
A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution...
7130950 Providing access to memory configuration information in a computer  
Client software stores an identifier corresponding to memory configuration data of interest and causes a software interrupt that requests a memory configuration read function. An interrupt read...
7130949 Managing input/output interruptions in non-dedicated interruption hardware environments  
Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment...
7117284 Vectored interrupt control within a system having a secure domain and a non-secure domain  
A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access...
7103758 Microcontroller performing safe recovery from standby mode  
A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is...
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