Matches 151 - 200 out of 232 < 1 2 3 4 5 >
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5974261 Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability  
A computer system has a processing unit with suspend/resume capability, a memory, and a hard disk drive. In response to a first command from the processor, the hard disk drive sends its status to...
5966543 Method of using collaborative spinlocks to provide exclusive access to a resource in a multiprocessor computer system  
A multiprocessor computing system has memory shared by all processors of the computing system and includes an symmetric multiprocessor (SMP) operating system and at least one external device...
5961585 Real time architecture for computer system  
A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To...
5944809 Method and apparatus for distributing interrupts in a symmetric multiprocessor system  
A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable...
5938758 Microprocessor having function of prefetching instruction  
A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first...
5931935 File system primitive allowing reprocessing of I/O requests by multiple drivers in a layered driver I/O system  
I/O systems of computers typically utilize multiple layered drivers to process I/O requests. I/O requests are passed from one driver to another in a defined sequence with each driver performing its...
5922032 Controller and method of controlling a hydraulic control network with latching valve  
A control method for managing a hydraulic control system of a vehicle is disclosed. The method includes the steps of scheduling the invocation of a plurality of vehicle functions through system...
5862340 Method operating in each node of a computer system providing and utilizing special records for collective communication commands to increase work efficiency at each node  
A testing apparatus designed to check the completion of a command issued earlier in a multiprocessing system having a plurality of nodes. During an initialization phase, each command has been...
5862389 Method and apparatus for selectively invoking a particular interrupt service routine for a particular interrupt request  
A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per...
5857108 Device and method for generating interrupts  
A device and method for generating an interrupt for a microcontroller (MCU) are disclosed. The device includes a first storing circuit for storing signals received/transmitted through a plurality...
5852743 Method and apparatus for connecting a plug-and-play peripheral device to a computer  
An apparatus for connecting a peripheral device to a computer is disclosed. The apparatus comprises a detection means on each peripheral input/output port for detecting a peripheral device. The...
5850555 System and method for validating interrupts before presentation to a CPU  
A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity...
5848277 Method for providing both level-sensitive and edge-sensitive interrupt signals on a serial interface between a peripheral and host  
A method or protocol for generating an Interrupt Signal for communication between a peripheral device and a host processor having either a level-sensitive or an edge-sensitive interrupt detector....
5819096 PCI to ISA interrupt protocol converter and selection mechanism  
An interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCI agent interrupts are processed by programmable...
5812837 Data processing apparatus for controlling an interrupt process and its method  
An interrupt processing apparatus is set if an interrupt factor occurs during execution of a moved instruction. The interrupt processing unit generates an interrupt single when processing after...
5805902 Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests  
An interrupt control circuit for use in a computer system has a CPU, a peripheral I/O device, and a bus having address lines for carrying signals to and from the peripheral I/O device. Interrupt...
5797021 Information processing apparatus for emulation  
An INTC and a CPU are interconnected via a bus. A first line through which an interrupt request signal is transferred to the CPU from the INTC, and a second line through which an interrupt...
5790872 Interrupt control handler for a RISC-type microprocessor  
The present invention relates to a data processing device that can perform independently a debug interruption process and a program interruption process. The data processing device consists of...
5784271 Data processor for interruption control between the CPU and the interruption controller  
A data processor comprises a CPU and an interruption controller connected with control signal line. The CPU changes signal level at a control signal line in response to an interruption request. The...
5778220 Method and apparatus for disabling interrupts in a highly pipelined processor  
A method and apparatus disables and re-enables an interrupt during the execution of certain I/O and memory operations in an out-of-order processor. The out-of-order processor executes...
5768599 Interrupt managing system for real-time operating system  
An interrupt managing system for a computer system in which resources are managed by a real-time operating system. The interrupt managing system has managed interrupt storage unit in which...
5764999 Enhanced system management mode with nesting  
An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a...
5761482 Emulation apparatus  
An access condition coincidence detecting circuit detects that an address stored in an access condition storing register 44 is outputted to an address bus 29. When a counter 46 counts a certain...
5754762 Secure multiple application IC card using interrupt instruction issued by operating system or application program to control operation flag that determines the operational mode of bi-modal CPU  
Multiple applications upon an IC microprocessor are protected with bi-modal CPU operation, either in application mode or system mode, using an operation flag determining the mode and a functional...
5740452 System for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors and methods therefor  
The present invention relates to a system and method for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors. The system...
5734910 Integrating multi-modal synchronous interrupt handlers for computer system  
A synchronous interrupt handler for a processing system executing multiple modes of operation employs a minimum number of lines of interrupt handler code written to execute at the "zeroth" level,...
5710843 Document processing apparatus having a communication/facsimile function with selective memory switching  
In a document processing method and apparatus, having both a communication function and a data processing function, when the communication function is performed during execution of the data...
5708818 Method and apparatus for real-time operation of a processor  
The hard-wired non-maskable interrupt (10) of a conventional processor (7), i.e. NMI or IOCHCK, is used to bypass programed interrupts to obtain immediate, predictable access to the processor and...
5701493 Exception handling method and apparatus in data processing systems  
A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the...
5694606 Mechanism for using common code to handle hardware interrupts in multiple processor modes  
An interrupt handler may be run in multiple processor modes on a data processing system having a processor for executing instructions and a memory for storing information. The sharing of interrupt...
5687380 Macro service processing of interrupt requests in a processing system where a single interrupt is generated for a plurality of completed transactions  
A data processing system is provided which includes a central processing unit connected to a memory and a plurality of peripheral units. When a single peripheral request is issued from one of the...
5684997 Integrated circuit design for handling of system management interrupts (SMI)  
An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit...
5682310 Computer system including in-circuit emulation mode for debugging system management software  
A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to...
5680624 Object oriented interrupt system  
A method and apparatus for an innovative, object-oriented hardware independent interface to the external world. The interrupt services are part of an overall IO model providing an object base IO...
5671422 Method and apparatus for switching between the modes of a processor  
A method for switching between a first mode and a second mode of a processor is provided. According to one embodiment of the invention, a computer system includes the processor coupled to a storage...
5664199 Microcomputer free from control of central processing unit (CPU) for receiving and writing instructions into memory independent of and during execution of CPU  
A microcomputer includes a program memory storing a string of instructions for a program, a central processing unit executing each instruction read out from the program memory, an instruction...
5655127 Method and apparatus for control of power consumption in a computer system  
A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The...
5652890 Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode  
A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves...
5642516 Selective shadowing of registers for interrupt processing  
Interrupts are prioritized such that selected interrupts use shadow registers to save the current state of the machine, whereas other interrupts use a software implemented interrupt service routine...
5640571 Interrupt steering for a computer system  
An interrupt request router is described. The interrupt request router stores a configuration value in a register, receives an interrupt request signal of a first plurality of interrupt request...
5630141 Hierarchical apparatus and method for processing device interrupts in a computer system  
A method and apparatus for an innovative hardware independent interface to the external world. The interrupt services are part of an overall I/O model providing an object base I/O system that...
5630090 Apparatus for and methods of providing a safe-stop mode for a microprocessor operating in a PSRAM-memory environment  
A microprocessor circuit including a microprocessor device and pseudo-static RAM memory further includes a switching circuit which is coupled to an NMI signal port and to a RESET signal port of the...
5619706 Method and apparatus for switching between interrupt delivery mechanisms within a multi-processor system  
A switching circuit and method for transparently switching between two interrupt delivery mechanisms; namely a first interrupt circuit and a second interrupt circuit. The first interrupt circuit is...
5619703 Apparatus and method for supporting multiple interrupt protocols with unequal number of interrupt request signals  
A peripheral device capable of generating interrupt request signals compliant with the Industry Standard Architecture (ISA) protocol, and the Peripheral Component Interconnect (PCI) protocol. The...
5560019 Method and apparatus for handling interrupts in a multiprocessor computer system  
An interrupt steering control mechanism includes an interrupt target register storing a code identifying a particular interrupt target processor to receive undirected interrupts within a multiple...
5555414 Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals  
A data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the hypervisor program includes one or more processors for...
5553293 Interprocessor interrupt processing system  
An interprocessor interrupt hardware unit ("IIU") for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in...
5551033 Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program  
A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves...
5542076 Method and apparatus for adaptive interrupt servicing in data processing system  
A method and apparatus for adaptive interrupt servicing is disclosed. The number of interrupts occurring within a predetermined time period is counted and stored as a value in an interrupt counter....
5535397 Method and apparatus for providing a context switch in response to an interrupt in a computer process  
A processor which includes at least a pair of call stacks and a pair of register files which may be utilized for running processes. The processor includes circuitry for detecting when an interrupt...
Matches 151 - 200 out of 232 < 1 2 3 4 5 >