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7617345 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts  
A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host...
7617428 Circuits and associated methods for improved debug and test of an application integrated circuit  
Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit...
7613861 System and method of obtaining error data within an information handling system  
A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management...
7610425 Approach for managing interrupt load distribution  
A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the...
7607133 Interrupt processing control  
A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is...
7606958 Interrupt control method, interrupt control apparatus and interrupt control medium  
Once accepting an interrupt, the control is such as to not accept any interrupt including that highest priority within the group to which the interrupt about to be processed belongs by referring...
7603673 Method and system for reducing context switch times  
An apparatus for managing resource in a multithreaded system, and attempting to increase the speed in which task switching occurs by controlling when thread state is stored to memory. The...
7596779 Condition management callback system and method of operation thereof  
A condition management callback system and method for use with a processor employing a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a condition...
7596792 Method and system for supporting a plurality of event types  
The present invention provides a method and system that is capable of identifying an event type from a plurality of event types to direct an event translator to determine an event occurrence based...
7590877 Computer system having multi-operation system and method for changing operating system in computer system  
Embodiments of a computer system and methods for changing operating systems (OSs) can perform a task switching into a different OS without checking a system reset or power off of the system. A...
7590982 System and method for virtualizing processor and interrupt priorities  
Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum...
7590990 Computer system  
A general-purpose OS (operating system) is used as a host OS and a real-time OS operating as one or more tasks on the host OS is used as a guest OS. An interrupt handler and a task on the host OS...
7587510 System and method for transferring data between a user space and a kernel space in a server associated with a distributed network environment  
A system (150) and method provide for the transfer of at least one packet (194) comprising data between a user space (152) and a kernel space (154) associated with a server (156) that is...
7587544 Extending secure digital input output capability on a controller bus  
Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.
7584316 Packet manager interrupt mapper  
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about...
7581052 Approach for distributing multiple interrupts among multiple processors  
A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the...
7577831 Relocating of system management interface code within an information handling system  
A method for relocating system management interface code in an information handling system which includes extracting a relocation table from the system management interface code, inserting a...
7574690 Graphical program which executes a timed loop  
A system and method for creating a graphical program operable to execute a timed loop. A loop may be displayed in the graphical program and configured with timing information in response to user...
7571020 Method and system for controlling process tools by interrupting process jobs depending on job priority  
By enabling an interleaved mode when supplying substrates from a plurality of load ports to a respective process module, a reduction of non-productive time of the process tool and/or a reduction...
7565471 Message signaled interrupt extended (MSI-X) auto clear and failsafe lock  
A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance...
7558428 Accelerated video encoding using a graphics processing unit  
The systems and methods described herein are directed at accelerating video encoding using a graphics processing unit. In one aspect, a video encoding system uses both a central processing unit...
7558897 Method for adopting an orphan I/O port in a redundant storage controller  
A method for adopting an orphaned I/O port of a storage controller is disclosed. The storage controller has first and second redundant field-replaceable units (FRU) for processing I/O requests and...
7552260 Method for dynamically arranging interrupt pins  
A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from...
7552261 Configurable prioritization of core generated interrupts  
A method and apparatus for generating an interrupt vector associated with either core (internal) generated or off-core (external) generated interrupts is provided. The apparatus includes a number...
7552477 Detecting return-to-LIBC buffer overflows via dynamic disassembly of offsets  
A method makes use of the fact that call modules, such as APIS, making calls to a critical operating system (OS) function are typically called by a call instruction while, in contrast, a RLIBC...
7549039 Generating an interrupt in a system having plural partitions that share a resource  
A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is...
7549005 System and method for managing interrupts  
Method and system for managing interrupts originating from multiple sources is provided. The method includes assigning interrupt sources to a group; notifying an adapter of interrupt groups;...
7546406 Virtualization of a global interrupt queue  
A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may...
7543095 Managing input/output interruptions in non-dedicated interruption hardware environments  
Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment...
7543306 Method, system, and program for handling device interrupts in a multi-processor environment  
Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of...
7536694 Exception handling in a multiprocessor system  
In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed...
7533201 Queue management mechanism in network processor wherein packets stored at memory device corresponds to addresses stored in plurity of queues within queue management  
According to one embodiment, a method is disclosed. The method includes selecting a first of a plurality of programmable interrupt enable registers, a controller determining for the first register...
7533207 Optimized interrupt delivery in a virtualized environment  
Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an...
7529876 Tag allocation method  
Embodiments of the present invention provide methods and systems for allocating multiple tags to multiple requesters in back to back clock cycles. A tag pool may be divided into a predetermined...
7529875 Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system  
Assigning interrupts for I/O devices among the nodes of NUMA systems is disclosed. At least one of the following is performed. First, interrupts for the devices are assigned among the nodes based...
7530066 Controlling snoop activities using task table in multiprocessor system  
An embodiment of the present invention includes a task table to store a task entry corresponding to a first task associated with a first processor. A snoop controller controls snooping an access...
7523297 Shadow scan decoder  
Methods and circuitry for processing a shadow scan instruction in a multi-threaded microprocessing environment include a bit sequence having a thread identifier, core identifiers and a shadow scan...
7516252 Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment  
Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and...
7516260 Method of communicating with embedded controller  
A method of communicating with an embedded controller is disclosed. The method is adapted for an Advanced Configuration and Power Interface specification (ACPI). According to the method, a busy...
7512730 Method for dynamically allocating interrupt pins  
A method for dynamically allocating interrupt pins is provided. The present method is used for allocating a plurality of interrupt pins of a control chip. In the present method, a hardware routing...
7503049 Information processing apparatus operable to switch operating systems  
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed by...
7502674 On-vehicle terminal system  
In an on-vehicle terminal system operating a plurality of operating systems, control of peripheral devices connected to the on-vehicle terminal system can be continued even if one of the operating...
7500036 Quad aware locking primitive  
A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a...
7500039 Method for communicating with a processor event facility  
A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility....
7500245 Changing code execution path using kernel mode redirection  
A mechanism for redirecting a code execution path in a running process. A one-byte interrupt instruction (e.g., INT 3) is inserted into the code path. The interrupt instruction passes control to a...
7493620 Transfer of waiting interrupts  
Apparatus and methods are provided for transferring interrupts. One embodiment of a computing device includes a first processor, a memory in communication with the first processor, and computer...
7493439 Systems and methods for providing performance monitoring in a memory system  
Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes...
7493435 Optimization of SMI handling and initialization  
A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may...
7493436 Interrupt handling using simultaneous multi-threading  
Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information...
7490214 Relocating data from a source page to a target page by marking transaction table entries valid or invalid based on mappings to virtual pages in kernel virtual memory address space  
According to one embodiment of the invention, a technique is provided for relocating the contents of kernel pages in a manner similar to techniques used for relocating the contents of user pages....