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7782783 Methods and systems for centralized link power management control (CLMC)  
A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored....
7783809 Virtualization of pin functionality in a point-to-point interface  
Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A...
7779178 Method and apparatus for application/OS triggered low-latency network communications  
A data buffer that is a target for data received over a communication channel is examined, and a device associated with the communication channel is polled, to find, process, and return data...
7779191 Platform-based idle-time processing  
A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the...
7774595 Computer security apparatus and method using security input device driver  
Provided is a computer security apparatus and a method using a security input device driver. Data inputted through a data input unit is directly encrypted at the security input device driver...
7774617 Masking a boot sequence by providing a dummy processor  
A mechanism is provided for masking a boot sequence by providing a dummy processor. With the mechanism, one of the processors of a multiprocessor system is chosen to be a boot processor. The other...
7770171 Plan executing apparatus, method of plan execution, and computer program product therefor  
A plan executing apparatus includes: an executing unit that executes a plan which is a sequence of processes; a processing state retaining unit that retains a processing state of a target object...
7765550 System for controlling context switch of deferred requests using counter and flag setting of thread accessing shared resource or entering code region  
In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context...
7765388 Interrupt verification support mechanism  
The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt...
7765351 High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips  
A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the...
7761637 Slave device with latched request for service  
Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate...
7752367 File-based access control for shared hardware devices  
An apparatus, program product and method effectively virtualize a hardware device shared between multiple processors by a file accessible by a processor such that access to the hardware device may...
7752615 Method and apparatus for deploying updates to a storage server management application  
According to an embodiment of the invention, a storage server management application (SSMA) includes scripting ability. The scripting ability allows functionality to be added to the SSMA by...
7747803 Device, system, and method of handling delayed transactions  
Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject...
7742905 Method and system for dynamically adjusting speed versus accuracy of computer platform simulation  
Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a...
7743193 Logic gateway circuit for bus that supports multiple interrupt request signals  
A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal...
7739438 Method for priority-encoding interrupts and vectoring to interrupt code  
A method for interrupt priority encoding and vectoring begins with reading pending interrupt bits from an interrupt status register. An entry in a table is located using the pending interrupt...
7734905 System and method for preventing an operating-system scheduler crash  
System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated...
7730250 Interrupt control circuit, circuit board, electro-optic device, and electronic apparatus  
An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that...
7730202 Dynamic interrupt timer  
A method of adjusting a timer is disclosed. The method includes adjusting a timer activation period based on a characteristic of a network and setting the timer using the timer activation period....
7725896 Periodic event execution control mechanism  
A scheduler schedules a plurality of periodic events. Each periodic event has an associated periodic interval of time and an associated set of services. The scheduler determines when one of the...
7721035 Multiprocessor system, processor and interrupt control method  
A first processor in a multiprocessor system for processing interrupts by a plurality of processors accepts an interrupt and executes first interrupt processing in accordance with the accepted...
7721033 Interrupt notification block  
An interrupt notification block stored in host memory is disclosed that contains an image of the interrupt condition contents that may be stored in a host attention register in a host interface...
7716407 Executing application function calls in response to an interrupt  
Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents...
7711885 Bus control apparatus and bus control method  
A bus control apparatus includes a plurality of blocks configured to output a write command for writing data into memory via a bus, and a bus connection control unit provided in correspondence...
7711881 Method for restoring system configuration information of a network attached storage  
A method for restoring system configuration information of a network attached storage includes the steps of: setting system configuration information of an network attached storage as a backup...
7707341 Virtualizing an interrupt controller  
In one embodiment, a method is contemplated. An interrupt is received in a processor from an interrupt controller. Responsive to receiving the interrupt, the interrupt is masked in the interrupt...
7707464 Timeout request scheduling using grouping and nonsynchronized processing to enhance performance  
An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling...
7702835 Tagged interrupt forwarding  
A system for tagged interrupt forwarding comprises a multiprocessor including a first and a second processor, an I/O device, and I/O management software. In response to an application I/O request,...
7698544 Automatic halting of a processor in debug mode due to reset  
Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor operates in one of a plurality of states...
7694055 Directing interrupts to currently idle processors  
Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of...
7689750 System and method to dynamically order system management interrupt handler dispatches  
Handling interrupts within an information handling system including entering into an interrupt management mode in response to receiving an interrupt, identifying at least one source of the...
7685607 General purpose embedded processor  
The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution...
7684884 Audio processor, input/output processing apparatus, and information processing apparatus  
There is provided an information processing apparatus in which a CPU and an audio processing unit are coupled by a bus. The audio processing unit includes a ring buffer that temporarily retains...
7680972 Micro interrupt handler  
A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task...
7680973 Sideband signal for USB with interrupt capability  
The invention provides for a sideband signal for the USB that has real-time interrupt capabilities. A system and method for hardware detection of an interrupt signal provides for the ability to...
7673088 Multi-tasking interference model  
The subject disclosure pertains to a multi-tasking interference system. A gatekeeper receives primary and secondary inputs, and a quantifier ascertains attention values associated with primary...
7664898 Method and system for efficient framing on addressed buses  
A framing mechanism may be provided that enables passing of messages over an addressed bus. This creates a form of information hiding, which passes information by converting an addressed bus...
7660323 Cascade control system for network units  
A network unit for the reception and forwarding of data packets and for use in a stack of similar units includes a data processor and cascade control logic for the exchange of control frames with...
7657683 Cross-thread interrupt controller for a multi-thread processor  
An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and...
7652978 Transmitting apparatus of OFDM system and method thereof  
The present invention relates to a transmitter in an OFDM system for improving the PAPR, and a method thereof. According to the exemplary embodiment of the present invention, channel encoding is...
7653912 Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations  
The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual...
7647589 Methods and systems for safe execution of guest code in virtual machine context  
Methods and systems for safe execution of guest code in virtual machine context are presented. A method for running a virtual machine in a computing system includes (a) launching a virtual machine...
7647509 Method and apparatus for managing power in a processing system with multiple partitions  
A processing system may include a first processing unit for a first partition and a second processing unit for a second partition. To support power management, an interrupt handler in the...
7644214 Information processing apparatus and task execution method  
An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified...
7644222 Low latency event communication system and method  
A low latency event communication system comprises a computer system having an Advanced Configuration and Power Interface (ACPI) namespace table with a Peripheral Component Interconnect (PCI)...
7640450 Method and apparatus for handling nested faults  
Apparatus and a method for handling nested faults including the steps of determining whether a fault is a first level fault, responding to a determination of a first level fault by saving a first...
7631114 Serial communication device  
The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the...
7627705 Method and apparatus for handling interrupts in embedded systems  
An Interrupt Processor is provided in an embedded system to handle interrupts generated in the system. The function of the interrupt processor is to handle interrupts and execute interrupt...
7624215 Interrupt controller  
An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request...