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7913017 Embedded system and interruption handling method  
An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In...
7913018 Methods and apparatus for halting cores in response to system management interrupts  
A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with...
7913009 Monitored notification facility for reducing inter-process/inter-partition interrupts  
Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between...
7908530 Memory module and on-line build-in self-test method thereof for enhancing memory system reliability  
A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit...
7899663 Providing memory consistency in an emulated processing environment  
Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory...
7899940 Servicing commands  
In a first aspect, a first method is provided for servicing commands. The first method includes the steps of (1) receiving a first command for servicing in a memory controller including a...
7899956 System and method of reducing the rate of interrupts generated by a device in microprocessor based systems  
Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device...
7895382 Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs  
A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring...
7890685 Multi-core data processor  
To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second...
7886177 Method and apparatus of collecting timer ticks  
Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or...
7886100 Information processing apparatus and SMI processing method thereof  
An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a...
7886101 Interruption control system and method  
An interruption control system includes two sense elements, a microprocessor, and a controller. The microprocessor includes two registers, two flip-latches, a multiplexer, and a microcontroller....
7886099 Systems and methods for providing a personal computer with non-volatile system memory  
In some embodiments, a system comprises a system memory module and an access card. The system memory module connects to a memory bus on a motherboard for a personal computer, while the access card...
7877753 Multi-processor system and program for causing computer to execute controlling method of interruption of multi-processor system  
A multi-processor system with a plurality of unit processors includes: a semaphore setting section for setting semaphores representing preferential right to the competing of resources to be able...
7873769 Micro controller unit (MCU) capable of increasing data retention time and method of driving the MCU  
A method of operating a micro controller unit including maintaining a stop mode operation when a battery level detected in response to a first interrupt signal input from an external source is in...
7873770 Filtering and remapping interrupts  
In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base...
7865854 Simultaneous parameter-driven and deterministic simulation with or without synchronization  
A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from...
7861024 Providing a set aside mechanism for posted interrupt transactions  
In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so...
7861072 Throwing one selected representative exception among aggregated multiple exceptions of same root cause received from concurrent tasks and discarding the rest  
Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler...
7853743 Processor and interrupt controlling method  
A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and...
7853814 Method and system for executing a power-cutoff-specific process within a specific processor of a multiprocessor system  
A multi processor system having a first processor; and one or more second processors is provided. Each of the one or more second processors is connected to the first processor by a dedicated...
7852777 Network hardware device  
A network hardware device of the invention includes a reception section receiving data from a network, and outputting a reception completion signal, a timer section measuring a preset time, and a...
7849236 Control equipment with communication apparatus  
A control equipment with a built-in communication apparatus is provided which realizes a delay required for communication without a software intervention while at the same time reducing a load of...
7849465 Programmable event driven yield mechanism which may activate service threads  
Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute...
7849246 I2C bus control circuit  
An I2C bus control circuit includes a continuous transmission control section in addition to a transmission control section, a sequence control section, a data line control section, and a clock...
7844809 Verifying a trusted SMI handler  
A trusted system management interrupt handler may be verified by first locating a signed system management interrupt handler image in system memory. The digital signature of the signed system...
7845006 Mitigating malicious exploitation of a vulnerability in a software application by selectively trapping execution along a code path  
A method of reducing the window of malicious exploitation between vulnerability publication and the installation of a software patch. One or more probe points are inserted into a code path in an...
7836450 Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts  
A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for...
7836227 Computer-readable recording medium having communication program recorded thereon, communication apparatus, and communication method  
A communication program causes a computer to perform communication processing of received packets in response to reception of interrupt processing, the interruption processing being a packet...
7836325 Power consumption reduction and quicker interruption response in an information processing device utilizing a first timer and a second timer wherein the second timer is only conditionally activated  
An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes...
7830925 Signal processing apparatus and methods  
A unified system of programming communication. The system encompasses the prior art (television, radio, broadcast hardcopy, computer communications, etc.) and new user specific mass media. Within...
7831980 Scheduling threads in a multi-processor computer  
Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of...
7827339 System management interrupt interface wrapper  
In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management...
7822899 Data processor and control system  
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to...
7818558 Method and apparatus for EFI BIOS time-slicing at OS runtime  
A method and apparatus is described herein for executing firmware tasks during OS runtime. A thread slices execution time among entries in a control structure, such as process control block (PCB),...
7818751 Methods and systems for scheduling execution of interrupt requests  
In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be...
7814252 Asymmetric multiprocessor  
An asymmetric multiprocessor capable of increasing a degree of freedom of distributed processing, minimizing a processing load on each processor (CPU), and achieving a large reduction in power...
7809876 Distributed real-time operating system  
A distributed control system and methods of operating such a control system are disclosed. In one embodiment, the distributed control system is operated in a manner in which interrupts are at...
7809875 Method and system for secure communication between processor partitions  
A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the...
7805555 Multiprocessor system  
The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt...
7805724 Apparatus, method and computer program for dynamic slip control in real-time scheduling  
An apparatus, method, and computer-readable program code for dynamically controlling slip is disclosed. The method monitors the time of an actual interrupt, wakes up, interacts with the physical...
7805725 System and method for synchronizing system modules  
A method and system is provided for automatically reassigning an interface card and devices associated with the interface card in a programmable logic controller system from a non-deterministic...
7802038 Communication steering for use in a multi-master shared resource system  
New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is...
7802042 Method and system for handling a management interrupt event in a multi-processor computing device  
A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores...
7802026 Method and system for processing frames in storage controllers  
Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR...
7797555 Method and apparatus for managing power from a sequestered partition of a processing system  
A processing system may include a first processing unit for a legacy partition and a second processing unit for a sequestered partition. In one embodiment, a first interrupt handler in the legacy...
7797465 Apparatus and methods to reduce frame interrupts in packet-based communication  
A core of a network includes a storage unit to store a plurality of parameters to receive and transmit data packets in a communication system. A program controls transfer of the data packets...
7797473 System for executing system management interrupts and methods thereof  
An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler,...
7793024 Method for utilizing a PCI-Express bus to communicate between system chips  
A method for command transmission between systems is introduced. The command transmission between the systems, such as a north bridge chip, a south bridge chip and a central processing unit (CPU),...
7788511 Method for measuring utilization of a power managed CPU  
An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while waiting for a wakeup. This invention...