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8463971 Approach for distributing interrupts from high-interrupt load devices  
A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the...
8463970 Method and system for managing sleep states of interrupt controllers in a portable computing device  
A method and system for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device are described. The method includes a processor...
8458386 Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements  
In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor...
8458508 Information processing device which specifies a waiting time until execution of a given event and makes a system call  
An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes...
8458387 Converting a message signaled interruption into an I/O adapter event notification to a guest operating system  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An...
8452907 Data processing apparatus and method for arbitrating access to a shared resource  
A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the...
8453002 Apparatus and method for controlling power state transitions based on timer events  
According to one embodiment, an electronic apparatus includes a first power saver, a second power saver and a controller. The first power saver executes switching from an operable condition to a...
8438323 Communication processing apparatus, communication processing method, control method and communication device of communication processing apparatus  
A communication processing apparatus (101) includes: a MAC unit (106) receiving a packet; a classification unit (107) classifying the received packet; a transfer control unit (104) transferring...
8438442 Method and apparatus for testing a data processing system  
A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the...
8433832 Control equipment with communication apparatus  
A control equipment with a built-in communication apparatus is provided which realizes a delay required for communication without a software intervention while at the same time reducing a load of...
8434098 Synchronizing split user-mode/kernel-mode device driver architecture  
A device driver includes a kernel mode and a user-mode module. The device driver may access device registers while operating in user-mode to promote system stability while providing a low-latency...
8429321 Request controller, processing unit, method for controlling requests and computer program product  
A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the...
8424015 Transactional memory preemption mechanism  
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction...
8423832 System and method for preventing processor errors  
A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor...
8424016 Techniques to manage critical region interrupts  
Briefly, techniques to manage interrupts and swaps of threads operating in critical region. In an embodiment, a thread is to be interrupted during a first critical region with an interrupt...
8413163 Program control device including per-timeslot switching of thread execution  
Provided is a program control device which switches, per timeslot, between threads to be executed. The program control device includes: a first interrupt creation unit which creates a first...
8412871 Information processing apparatus, information processing method, and program  
The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary...
8397007 Interrupt moderation  
A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed...
8392643 Data processing device, semiconductor integrated circuit device, and abnormality detection method  
A data processing device for detecting the abnormal operation of a CPU is provided. The data processing device comprises a CPU, an interrupt counter, and a counter-abnormal-value detection...
8392629 System and methods for using a DMA module for a plurality of virtual machines  
A system comprising a plurality of virtual machines executed by a computing system; and an adapter; wherein the adapter includes a direct memory access (DMA) module for transferring control blocks...
8392640 Pre-memory resource contention resolution  
Techniques are disclosed relating to resource contention resolution in a pre-memory environment. Prior to system memory being accessible, a resource control processing element controls access to a...
8392641 Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set  
Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data...
8392644 System and method for automatic hardware interrupt handling  
A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states...
8386704 Techniques for improving hard disk drive efficiency  
A host operating system (OS) can function as a task under a disk drive operating system. The host OS and the disk drive operating system can be run on a single processor. The processor is able to...
8386684 Data processing system and method of interrupt handling  
A data processing system is provided which comprises at least two processing units (100, 101, 102) each for executing a plurality of tasks and an interrupt handling unit (200) for receiving an...
8380906 Method and system for implementing interrupt service routines  
Methods, computer-readable media, and systems for interrupt handling in Java™ are provided. In some illustrative embodiments, a method for interrupt handling in Java software that executes on a...
8380908 Emulation of an input/output advanced programmable interrupt controller  
Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt...
8380907 Method, system and computer program product for providing filtering of GUEST2 quiesce requests  
A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor...
8375155 Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer  
Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of...
8370618 Multiple platform support in computer system firmware  
Technologies are provided herein for multiple platform support in a computer system firmware. A firmware is built for each hardware platform to be supported. At built time of the firmware for each...
8370553 Formal verification of random priority-based arbiters using property strengthening and underapproximations  
A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a...
8364876 Computer system  
A computer system is provided that can realize polling without increasing the processing burden on the processor. Data is read by a polling unit during a prescribed period from a prescribed...
8364877 Implementing gang interrupts  
A method includes receiving a first interrupt request from a first device instance of a plurality of device instances. The first interrupt request is requesting an interrupt of a processor. The...
8355150 Information processing apparatus, program product, and recording medium capable of appropriately executing an output process even when uninterpretable information is included in output setting information  
A disclosed information processing apparatus, which is connected to an output device, detects, from output setting information, an uninterpretable setting that is uninterpretable by the...
8356299 Interrupt processing method and system  
A method for interrupt processing includes setting a buffer for buffering data packets received by a front-end or back-end of the virtual machine and setting a timer for timing data buffering...
8352804 Systems and methods for secure interrupt handling  
The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service...
8352965 Transmission method and circuit device capable of automatic transmission interface selection  
A circuit device capable of automatic transmission interface selection and associated method are provided. The circuit device includes a first interface port, a second interface port, a first...
8341438 Information processing device for assigning interrupts to a first CPU or a second CPU based on a sleeping state  
An information processing device of the present invention comprises a main CPU capable of taking at least two states which are an operating state and a sleeping state, a sub-CPU having power...
8332877 Coordinated actions of kernel and userspace components  
A system for and method of coordinating actions of components between userspace and kernel are described. The system comprises a processor; zero or more hardware components coupled with the...
8323024 System for trouble shooting and controlling signals to and from an aircraft simulator  
A system for controlling signals coming from or going to an aircraft simulator has a first slave circuit and a second slave circuit. The second slave circuit is used to monitor signals coming from...
8315173 Transmission apparatus and method for distributed management thereof  
Disclosed is a transmission apparatus in which a plurality of elements implement virtually one apparatus. Each element includes at least one main signal package and a monitor control package that...
8316172 Interruption facility for adjunct processor queues  
Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption...
8312195 Managing interrupts using a preferred binding between a device generating interrupts and a CPU  
A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The...
8307141 Multi-core processor, control method thereof, and information processing apparatus  
A multi-core processor which includes a plurality of processor dies. The multi-core processor has a first processor core which processes a first task and a second processor core which processes a...
8301917 Method and apparatus for managing power from a sequestered partition of a processing system  
A processing system may include a first processing unit for a legacy partition and a second processing unit for a sequestered partition. In one embodiment, a first interrupt handler in the legacy...
8301873 Method and computer system for thermal throttling protection  
An automatic thermal throttling protection method is described. a computer system executes a main BIOS for initializing an embedded controller when the computer system is power on or boots. And...
8296490 Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system  
Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered...
8286162 Delivering interrupts directly to a virtual processor  
Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt...
8271711 Program status detecting apparatus and method  
A method for a computer including a processor that is capable of counting invalidation of translation lookaside buffers and generating an interrupt at the occurrence of the invalidation, the...
8271978 Virtualization event processing in a layered virtualization architecture  
Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and...