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8620991 Technologies for detecting erroneous resumptions in a continuation based runtime  
Technologies for enabling a continuation based runtime to accept or reject external stimulus and, in addition, to determine if an external stimulus may be valid for processing at a later point in...
8621140 Flash memory apparatus for controlling operation in response to generation of interrupt signal and method of controlling the same  
Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more...
8615671 Techniques for managing lower power states for data links  
Techniques for managing lower power states for data links are described. An apparatus may comprise a memory unit to store a device connection manager for a controller of a bi-directional serial...
8612661 Interrupt-notification control unit, semiconductor integrated circuit and methods therefor  
An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the...
8612973 Method and system for handling interrupts within computer system during hardware resource migration  
A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address...
8612660 Interrupt latency measurement  
A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator...
8610911 Printing device, printing system, printing control method and recording medium  
A conversion unit converts a command part of an image inclusion command into an internal command. A first memory unit stores an image non-inclusion command and the internal command converted by...
8606975 Managing interrupts in a virtualized input/output device supporting multiple hosts and functions  
Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g.,...
8599395 Printing device, printing control method and recording medium  
A LAN control unit receives print data from a client device or the like. An input job storage unit registered on a hard disk a series of PDL commands included in the print data received. An input...
8601193 Performance monitor design for instruction profiling using shared counters  
Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is...
8601194 On-demand interrupt vector allocation based on activity detection  
A method and system for dynamically allocating interrupt vectors on demand. A computer system measures a rate of activities associated with an event. Based on the rate of activities, the computer...
8601497 Converting a message signaled interruption into an I/O adapter event notification  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the...
8578080 Secure handling of interrupted events utilizing a virtual interrupt definition table  
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still...
8578368 Injecting a file from the bios into an operating system  
Techniques for the BIOS to install a file into the runtime environment of an operating system of a computer. A system management interrupt (SMI) handler, resident within the BIOS, receives a first...
8572295 Bus traffic profiling  
Methods and systems for analyzing bus traffic in a target device, such as a system on-a-chip (SOC) comprises capturing a processor event and generating an interrupt based on a threshold associated...
8572159 Managing device models in a virtual machine cluster environment  
Machine-readable media, methods, apparatus and system are described. In some embodiments, a client platform may determine that an input/output operation related to a hardware device may happen in...
8572635 Converting a message signaled interruption into an I/O adapter event notification  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the...
8572729 System, method and computer program product for interception of user mode code execution and redirection to kernel mode  
A system, method and computer program product are provided. In use, code is executed in user mode. Further, the execution of the code is intercepted. In response to the interception, operations...
8566492 Posting interrupts to virtual processors  
Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up...
8560748 Information processing system including interrupt processing function  
An interrupt control circuit asserts a remap signal in response to an interrupt request from a low-speed slave to a processor, and reads information stored in an information register of the...
8560749 Techniques for managing power consumption state of a processor involving use of latency tolerance report value  
Techniques are described for determining a temporary latency tolerance report (tLTR) value. A processing unit has to respond to a device interrupt within a duration specified by tLTR to ensure no...
8554968 Interrupt technique for a nonvolatile memory controller  
A nonvolatile memory controller processes a nonvolatile memory command and generates a completion status for the nonvolatile memory command. The nonvolatile memory controller transmits the...
8549200 Multiprocessor system configured as system LSI  
A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor...
8544022 Transactional memory preemption mechanism  
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction...
8527682 Bus controller, bus communication system, and bus control method  
It is an object to prevent a command-issuing interval from being fixed and then avoid a situation where a target always returns a retry by varying a timing of a command-issuing request (i.e., a...
8522239 Methods and systems for safe execution of guest code in virtual machine context  
System for safe execution of guest code in virtual machine context includes (a) a virtual machine monitor (VMM) that uses hardware virtualization means for handling potentially unsafe...
8521935 Portable electronic apparatus, control method for portable electronic apparatus, and IC card  
According to one embodiment, a portable electronic apparatus includes a receiving section configured to receive from an external device an instruction for a transition from an active state to a...
8510492 System and method for communication handshaking between a master processors and a slave processor  
System and method for handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor are described. In one...
8510491 Method and apparatus for efficient interrupt event notification for a scalable input/output device  
A method and apparatus for efficient interrupt event notification for a scalable input/output device in a network system. A network interface unit is operably connected to a plurality of...
8504751 Integrated circuit package with multiple dies and interrupt processing  
A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and...
8499111 Information processing apparatus and clock signal controlling method controlling whether clock signal provided to interrupt signal controlling device  
An information processing apparatus includes an interrupting signal control device including a mask controller, the mask controller controlling whether or not to mask at least one interrupting...
8499140 Dynamically adjusting pipelined data paths for improved power management  
A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The...
8495217 Mechanism for preventing client partition crashes by removing processing resources from the client logical partition when an NPIV server goes down  
With N_Port ID Virtualization (NPIV), a managed system can be configured so that multiple logical partitions (LPARs) can access independent physical storage through the same physical fibre channel...
8495261 Redispatching suspended tasks after completion of I/O operations absent I/O interrupts  
Input/output (I/O) interrupts are avoided at the completion of I/O operations. A task requests (implicitly or explicitly) an I/O operation, and processing of the task is suspended awaiting...
8489788 Data processor and control system  
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to...
8489787 Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors  
Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a...
8489789 Interrupt virtualization  
In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an...
8484389 AV renderer peripheral with dual inerrupt lines for staggered interrupts  
An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two...
8484648 Hardware multi-threading co-scheduling for parallel processing systems  
A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware...
8484696 Secure game download  
A method for gaming terminals, gaming kiosks and lottery terminals to ensure that the code-signing verification process of downloaded game software can be trusted. Drivers independently developed...
8484396 Method and system for conditional interrupts  
A method for issuing interrupts includes a receiving communication adapter receiving a first remote directed memory access (RDMA) write with immediate, identifying a completion queue descriptor...
8478923 Interrupt suppression by processing just first interrupt of a same type  
A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts...
8478922 Controlling a rate at which adapter interruption requests are processed  
The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on...
8479184 General purpose emit for use in value profiling  
An information handling system includes a memory, a processor, and an instruction tracking unit. The processor executes program code and, while the program code executes, the instruction tracking...
8478920 Controlling data stream interruptions on a shared interface  
A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are...
8473647 Methods and apparatus for decreasing power consumption and bus activity  
Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, a client-driven host device state machine switches...
8473662 Interrupt-handling-mode determining method of embedded operating system kernel  
Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device....
8468284 Converting a message signaled interruption into an I/O adapter event notification to a guest operating system  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An...
8468524 Inter-virtual machine time profiling of I/O transactions  
Disclosed is a virtual machine system where hardware timer interrupts are processed by a first virtual machine. The first virtual machine writes a timer value to a shared memory location while...
8463969 Extended message signal interrupt  
Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are...