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6240483 System for memory based interrupt queue in a memory of a multiprocessor system  
An interrupt mechanism which reduces or eliminates the need for an interrupt status register while at the same time provides suitable information to a host or other processor with respect to the...
6240470 Magnetic disk control unit, and firmware active-interchange method therefor  
The present invention relates to a magnetic disk control unit which can accomplish active interchange of firmwares. Thus, in this invention, a firmware constituting the magnetic disk control unit...
6240493 Method and apparatus for performing access censorship in a data processing system  
Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against...
6237058 Interrupt load distribution system for shared bus type multiprocessor system and interrupt load distribution method  
An interrupt load distribution system for a shared bus type multiprocessor system includes a processor statistical information table for storing processor statistical information consisting of...
6223245 Device and method for generating interrupt  
A device and method for generating non-false interrupt signals are disclosed. They discriminate between noise and real signals from the interrupt sources. The device includes: plural signal...
6219741 Transactions supporting interrupt destination redirection and level triggered interrupt semantics  
In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the...
6219742 Method and apparatus for artificially generating general purpose events in an ACPI environment  
A hardware implementation of the General Purpose Event status register supports the ability to assert, under software control, individual General Purpose Event status bits in a General Purpose...
6219743 Apparatus for dynamic resource mapping for isolating interrupt sources and method therefor  
An apparatus and method of dynamic resource mapping for isolating interrupt sources is implemented. Each interrupt source is provided with a unique identifier. The identifier is mapped to an...
6212594 Timer with fixed and programmable interrupt periods  
A method for causing two programmable interrupts to take place is described herein, using a counter having an output having an adjustable period, a first register which controls the length of the...
6209019 Data processing system, computer network, and data processing method  
It is an object of this invention to provide a data processing system, computer network, and data processing method which enable alternate programs to run without degrading the system processing...
6209051 Method for switching between multiple system hosts  
In a method for switching between multiple system hosts (154,164,174,184) on a CompactPCI bus (110,120), a hot swap controller (166,186) provides to a special arbiter (820) a high priority request...
6208361 Method and system for efficient context switching in a computer graphics system  
The present invention comprises a system for implementing efficient context switching in a graphics computer system including a processor subsystem and a graphics pipeline. The system of the...
6205509 Method for improving interrupt response time  
A method and apparatus for rapidly detecting the source of an interrupt. A multi-bit interrupt state register is provided which registers the occurrence of an interrupt in response to an interrupt...
6205508 Method for distributing interrupts in a multi-processor system  
An interrupt messaging scheme for a multiprocessing computer system where a dedicated bus to carry interrupt messages within the multiprocessing system is eliminated. Instead, an interconnect...
6205518 Apparatus and method for reducing power consumption in a data processor executing an application code  
Apparatus and methods are described for reducing power consumption in a processor. The processor includes a source of microcode instructions, a microcode instruction decode circuit, control...
6205507 Memory coherency in a processor-to-bus cycle in a multi-processor system  
In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an...
6192425 Personal computer interrupt line sharing circuit with active interrupt line monitoring, and method for sharing a common interrupt line by active monitoring  
In an interrupt line sharing circuit for a personal computer system, which has a plurality of instruments and one common interrupt line provided in common to the plurality of instruments, a...
6192455 Apparatus and method for preventing access to SMRAM space through AGP addressing  
A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and...
6192442 Interrupt controller  
An interrupt controller includes conductors for receiving interrupt request signals, a memory, a register and control logic. Each of the interrupt request signals are capable of indicating an...
6192440 System and method for dynamically selecting interrupt storage time threshold parameters  
A system and method for dynamically calculating the maximum amount of time a peripheral component event can be stored before generating a corresponding interrupt. Specifically, in this embodiment,...
6192439 PCI-compliant interrupt steering architecture  
An interrupt steering architecture that enables an intelligent peripheral device to process interrupts from PCI devices associated with a PCI bus is disclosed. The interrupt steering architecture...
6189070 Apparatus and method for suspending operation to read code in a nonvolatile writable semiconductor memory  
A method and apparatus manages data and reads code from a nonvolatile writeable memory. In a nonvolatile writeable system, interrupts are disabled. A non-read operation is initiated in the...
6189065 Method and apparatus for interrupt load balancing for powerPC processors  
Interrupts from an I/O subsystem are first directed to a single processor in a multiple superscalar processor data processing system. If an interrupt load on the processor is sufficiently high,...
6189093 System for initiating exception routine in response to memory access exception by storing exception information and exception bit within architectured register  
A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory...
6182179 System that is able to read and write using a transmission medium and is able to read stored information via a model information structure using a different transmission medium  
A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined...
6173339 System for monitoring execution of commands from a host for shared I/O devices by setting a time-out period based on control parameters sent by the host  
A command execution monitoring system includes a first unit which retains control parameters of an operation control command sent by one of host computers, the control parameters including an...
6170025 Distributed computer system supporting remote interrupts and lock mechanism  
A distributed computer system includes a host CPU, a network/host bridge, a network/I/O bridge and one or more I/O devices. The host CPU can generate a locked host transaction, which is wrapped in...
6170033 Forwarding causes of non-maskable interrupts to the interrupt handler  
The present invention relates to a method and apparatus for directing causes of non-maskable interrupts. The apparatus determines whether a computer system is designed to handle an alternative...
6167479 System and method for testing interrupt processing logic within an instruction processor  
A system and method is provided for selectively injecting interrupts within the instruction stream of a data processing system. The system includes a programmable storage device for storing...
6167425 System for implementing a real time control program in a non-real time operating system using interrupts and enabling a deterministic time charing between the control program and the operating system  
The invention pertains to a method and apparatus for implementing a real time control program in a non-real time operating system running on a processor of a PC system, wherein a change of...
6167480 Information packet reception indicator for reducing the utilization of a host system processor unit  
A reception indicator is within a network peripheral that receives information packets for a host system from a communications network. The reception indicator of the present invention allows the...
6163829 DSP interrupt control for handling multiple interrupts  
A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing...
6154832 Processor employing multiple register sets to eliminate interrupts  
A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other...
6151664 Programmable SRAM and DRAM cache interface with preset access priorities  
A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on...
6148360 Nonvolatile writeable memory with program suspend command  
A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control...
6148361 Interrupt architecture for a non-uniform memory access (NUMA) data processing system  
A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The...
6145030 System for managing input/output address accesses at a bridge/memory controller  
An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O...
6145047 Circuit and method for converting interrupt signals from level trigger mode to edge trigger mode  
Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge...
6145007 Interprocessor communication circuitry and methods  
A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a...
6131137 Drive control unit and optical memory apparatus  
An optical memory apparatus, in which an ODC section generates an interruption according to an instruction from an upper system, an ODD section provides drive controls over a memory apparatus...
6128691 Apparatus and method for transporting interrupts from secondary PCI busses to a compatibility PCI bus  
During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication...
6125236 Method and apparatus for providing user control of multimedia parameters  
A computer system for providing user control of multimedia output parameters. The computer system includes a central processing unit (CPU) coupled to a memory unit. The memory unit includes a...
6125456 Microcomputer with self-diagnostic unit  
To perform the self-diagnostic of the CPU, the CPU monitor macro service is activated in response to the interrupt signal from the external. In the CPU monitor macro service, according to the CPU...
6125443 Interrupt processing system and method for information processing system of pipeline control type  
An interrupt processing system and method for an information processing system of pipeline control type are disclosed. The occurrence of an exception is detected for each plurality of instructions...
6122679 Master DMA controller with re-map engine for only spawning programming cycles to slave DMA controllers which do not match current programming cycle  
A computer system implementing a distributed direct memory access architecture is disclosed. The computer system includes a re-map engine that includes control logic and a shadow register for each...
6122700 Apparatus and method for reducing interrupt density in computer systems by storing one or more interrupt events received at a first device in a memory and issuing an interrupt upon occurrence of a first predefined event  
A method and apparatus for reducing interrupt density in a computer system. One or more interrupt events received at a first device are stored in a memory and an interrupt is issued from the first...
6122701 Device volume control in multimode computer systems  
A volume control handler allows users to dynamically alter the volume level of an audio device when the device is under control of a DOS mode application. The dynamic volume adjustment is...
6115778 Method and apparatus for handling interrupts through the use of a vector access signal  
A control system comprises an interrupt controller, having vector access signal output mechanism for outputting a vector access signal, which is activated when a start address is read out from a...
6115776 Network and adaptor with time-based and packet number based interrupt combinations  
A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates...
6115777 LOADRS instruction and asynchronous context switch  
A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a...