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6718413 Contention-based methods for generating reduced number of interrupts  
Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer...
6715005 Method and system for reducing latency in message passing systems  
A method and system for synchronizing message transfers from a sender to a receiver, such that message latency and overhead processing are minimized. A next inter-message arrival delay is...
6715017 Interruption signal generating apparatus  
An interruption signal generating apparatus comprises a counter unit counting a predetermined time interval and outputting a count-up signal indicating the end of the counting; a first generating...
6711642 Method and chipset for system management mode interrupt of multi-processor supporting system  
A method and a chipset for supporting a system management mode interrupt of a multi-processor system. While the central processing is accessing the specified input/output port defined by the...
6711643 Method and apparatus for interrupt redirection for arm processors  
Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an...
6711641 Operation processing apparatus  
The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a...
6708244 Optimized I2O messaging unit  
A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more...
6704823 Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing  
A method and an apparatus is present for dynamically allocating a set of output interrupt lines at a host adapter to a set of input interrupt lines for card slots controlled by the host adapter....
6704863 Low-latency DMA handling in pipelined processors  
A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids...
6701413 Disk drive performing a read-ahead operation of the data from the disk  
In a disk drive, a read-ahead operation is prevented from being aborted due to an interrupt such as an error, to prevent the operation of a host device from stopping and to enhance reliability....
6697959 Fault handling in a data processing system utilizing a fault vector pointer table  
A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The...
6694398 Circuit for selecting interrupt requests in RISC microprocessors  
An apparatus and method for prioritizing interrupt requests in a RISC processor. By utilizing hardware to prioritize the requests, processor time is reduced. The acknowledge signal from a priority...
6691195 Compact diagnostic connector for a motherboard of data processing system  
A compact connector for a data processing system motherboard facilitates the performance of diagnostics on data processing system components. The connector includes first, second, and third...
6687845 Fault vector pointer table  
A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The...
6684281 Fast delivery of interrupt message over network  
A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt...
6681281 System and method for implementing a multi-level interrupt scheme in a computer system  
A system and method for implementing a multi-level interrupt scheme in a computer system is provided. Bus devices and a bus controller may be coupled to a shared bus in a computer system. The bus...
6675191 Method of starting execution of threads simultaneously at a plurality of processors and device therefor  
In a multi-processor system in which a plurality of threads to be simultaneously executed at a plurality of processors are stored as one thread set at a context area one-to-one corresponding to a...
6665752 Interrupt driven interface coupling a programmable media access controller and a process controller  
An interrupt driven interface coupling a programmable media access controller (MAC) and a process controller. The interrupt driven interface is operable within a cable modem system. The...
6665761 Method and apparatus for routing interrupts in a clustered multiprocessor system  
A method and apparatus for increasing the routing bandwidth of interrupts between cluster manager devices in a clustered multiprocessor system is disclosed. This is accomplished by providing...
6658515 Background execution of universal serial bus transactions  
A method, computer program product and computer system that features intermittently entering the system management mode of a processor to commence and terminate I/O activity between external...
6658514 Interrupt and control packets for a microcomputer  
A computer system comprises on-chip a CPU with at least one different module, both having circuitry to generate two types of address request packets, one being a control command packet to which a...
6654896 Handling of multiple compliant and non-compliant wake-up sources in a computer system  
A system and method are disclosed for handling devices that assert a wake-up signal in an improper fashion. It is observed that any wake-up signals that remain asserted as the computer system...
6654839 Interrupt controller, asic, and electronic equipment  
An interrupt controller, ASIC, and electronic equipment are provided that make it possible to branch directly to interrupt processing routines at a plurality of locations. When an interrupt...
6643724 Method and apparatus for interrupt routing of PCI adapters via device address mapping  
A method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to...
6640276 Bus system and method for achieving a stable bus redundancy  
A bus system interconnected to a coupling module to form a ring structure for reasons of redundancy, whereby a linear structure of the bus (1) is achieved through a partition (9) in the coupling...
6640274 Method and apparatus for reducing the disk drive data transfer interrupt service latency penalty  
A method and apparatus for reducing the disk drive data transfer interrupt service latency penalty is described. The method comprises beginning a data transfer between a disk drive and a host...
6636916 Assigning PCI device interrupts in a computer system  
A method and apparatus for assigning interrupts to devices on a PCI bus in a computer system in which a plurality of address lines are channeled through a multiplexer to a PCI device on the PCI...
6631475 Microcomputer including system for controlling and maintaining the electric potential of an input terminal to improve interrupt response time  
A microcomputer has an electric potential control unit, a signal generation unit, and a timing signal generation circuit. The electric potential control unit includes a transistor which controls...
6631434 Dynamic early indication system for a computer  
A dynamic early indication system for a computer includes a processor subsystem logic that performs a subsystem function, an early indicator, indication logic, and a driver that is executed by the...
6629179 Message signaled interrupt generating device and method  
The present invention provides a bridge device and a method for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a...
6629252 Method for determining if a delay required before proceeding with the detected interrupt and exiting the interrupt without clearing the interrupt  
A method and system for servicing an interrupt is presented. An interrupt handler associated with a detected interrupt is invoked, and a determination is made as to whether to instantiate a delay...
6625679 Apparatus and method for converting interrupt transactions to interrupt signals to distribute interrupts to IA-32 processors  
An apparatus and method for distributing interrupts to IntelĀ® Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system...
6625637 Method and apparatus for synthesizing communication support based on communication types of application  
Disclosed are method and apparatus for synthesizing communication support based on communication types of an application. In the integrated circuit design method, an application schedule is...
6622185 System and method for providing a real-time programmable interface to a general-purpose non-real-time computing system  
A system and method providing read-time external signals to and from a gaming application executing within a platform independent programming environment on a computing system. The system has an...
6622191 Computer system  
A PCI-PCI bridge which connects a primary PCI (Peripheral Component Interconnect) bus and a secondary PCI bus comprises two physically different controllers, a primary PCI serial transfer...
6622192 Method of shutting down a server in safety  
This invention relates to a method of shutting down a server, more particularly, to a method of shutting down the server safely. The present invention uses a pre-setup normal shutting down...
6615288 Generating system management interrupt in response to usb controller signal and processing interrupt routine in upper most level of system memory  
Systems and methods for enabling computer system devices and components are disclosed. A method for use in a computer system having a processor includes receiving an input from a device coupled to...
6615303 Computer system with multiple operating system operation  
A computer system is provided with a scheme to making the input and output device provided in a computer in common for a plurality of operating system, in a multiple operating system control unit...
6615304 Processing unit in which access to system memory is controlled  
Has an instruction issuing unit that monitors a change in a memory access sequencing model as well as monitoring a change in an interruption level. When the memory access sequencing model has been...
6606687 Optimized hardware cleaning function for VIVT data cache  
A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84)...
6606676 Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
6606677 High speed interrupt controller  
A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its...
6604161 Translation of PCI level interrupts into packet based messages for edge event drive microprocessors  
Translation of PCI level interrupts into packet based messages for edge event drive microprocessors includes, a bridge device receiving interrupts via an interrupt line from one or more PCI...
6584511 Loop initialization procedure exception handling for fibre channel transmissions  
A fiber optic channel loop provides a transmission path between a computer platform and a multiple number of peripheral devices. When any change occurs in the number of connected peripheral...
6584528 Microprocessor allocating no wait storage of variable capacity to plurality of resources, and memory device therefor  
A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the...
6581120 Interrupt controller  
An interrupt controller can execute a faster interrupt service routine after an occurrence of the interrupt by writing branch instructions upon initialization of the computer environment in...
6581119 Interrupt controller and a microcomputer incorporating this controller  
To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers...
6574694 Interrupt optimization using time between succeeding peripheral component events  
A method and system for efficiently servicing a peripheral component event. In one embodiment of the present invention, peripheral component events are coalesced. The time interval between...
6571206 Apparatus and method for emulating an I/O instruction for the correct processor and for servicing software SMI's in a multi-processor environment  
A method for controlling I/O in a multi-processor environment, comprising the steps of: determining if an I/O instruction requiring an interrupt is being executed by one of the processors in the...
6567874 Signal switch apparatus  
A signal switch apparatus includes a signal switch component, which is connected to a interrupt controller, a high level signal, and two PCI slots. Only when the SCSI card is inserted into the...