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6820155 Interruption managing device and interruption managing method  
An interrupt management section 103 for holding interrupt acceptance possibility states prepared for each of interrupt sources 121 to 122, and an interrupt mask cancellation section 104 for...
6820154 System and method for servicing interrupts  
Disclosed are a system and method of selectively awaking processes in response to an interrupt condition. A processing system may host a plurality of processes where each process is associated...
6816935 Interrupt and status reporting structure and method for a timeslot bus  
An interrupt and status reporting method and structure for a timeslot bus communications protocol. In one embodiment, a peripheral bus is a timeslot bus configured to transmit information across...
6816809 Hardware based utilization metering  
A hardware based utilization metering device, and a corresponding method are used in a computer system having one or more central processor units (CPUs) to provide a measure of CPU utilization....
6813728 Method and a device for checking the functioning of a computer  
A method and a device for checking the functioning of a computer are proposed, the computer in a normal operating state having access to the working memory via bus lines. For the purposes of...
6813665 Interrupt method, system and medium  
An interrupt method, system, and/or medium may comprise generating a load balancing value that helps balance servicing of interrupts among processors.
6807595 Mobile communication device having a prioritized interrupt controller  
A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the...
6799316 Virtualizing hardware with system management interrupts  
Initially, a SMI trap detects an application accessing a memory location associated with a physical hardware device. The SMI trap receives the device address for the address bus and compares that...
6798708 Memory controller and serial memory  
In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active...
6799317 Interrupt mechanism for shared memory message passing  
A method for transparently handling messages originating from local shared memory and from an external source. A device driver allows the local sender to identify and wake up a waiting receiver...
6795884 Read-only memory based circuitry for sharing an interrupt between disk drive interfaces  
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry...
6792483 I/O generation responsive to a workload heuristics algorithm  
An apparatus, method and program product for use with a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by said processor for storing...
6792491 Invoking ACPI source language code from interrupt handler  
In one embodiment of the invention, an embedded controller receives an interrupt command and a query number from a system management interrupt (SMI) handler. The embedded controller generates a...
6792492 System and method of lowering overhead and latency needed to service operating system interrupts  
A method for achieving low overhead for operating system (“OS”) interrupts is described. In a preferred embodiment, when an interrupt occurs, a lightweight interrupt handler is used to acknowledge...
6789142 Method, system, and program for handling interrupt requests  
Provided are a method, system, and program for handling interrupts. A request is received as to whether a device transmitted an interrupt and a determination is made as to whether the device...
6785893 Operating system event tracker having separate storage for interrupt and non-interrupt events and flushing the third memory when timeout and memory full occur  
A system and method for logging events processed by an operating system is provided. The events logged can include interrupt and non-interrupt events, and can include user-defined events....
6782432 Automatic state savings in a graphics pipeline  
A method, apparatus, and system are described for processing an operation code (op-code) to be transmitted over a data path of a graphics pipeline. If the op-code comprises context state...
6779065 Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads  
The present invention provides a mechanism for handling interrupts on a processor that supports multiple-threads concurrently. The processor's resources are allocated to provide multiple logical...
6779054 Method and apparatus for operating a network controller  
In one embodiment, an apparatus is described. The apparatus includes an input/output (I/O) device that is capable of being coupled to a computing system. The device is configured such that, in...
6775729 PERIPHERAL DEVICE, PERIPHERAL DEVICE CONTROL METHOD, PERIPHERAL DEVICE CONTROL SYSTEM, STORAGE MEDIUM FOR STORING PERIPHERAL DEVICE CONTROL PROGRAMS, SENDING DEVICE FOR SENDING PERIPHERAL DEVICE CONTROL PROGRAMS, AND PERIPHERAL DEVICE CONTROL PROGRAM PRODUCT  
A peripheral device is connected to an information processing device, and in the event that an interruption job is input from the information processing device while the peripheral device is...
6775721 Method and system for handling a data stream from optical media utilizing automatic link sector detection  
The present invention provides an improved method and system for link detection and handling. The method includes detecting one of the plurality of link sectors; generating an interrupt signal;...
6775728 Method and system for concurrent handler execution in an SMI and PMI-based dispatch-execution framework  
A method and system that enables concurrent event handler execution in a system management interrupt (SMI) and processor management interrupt (PMI)-based dispatch-execution framework to service an...
6772257 Method and apparatus for processing interrupts  
Briefly, in accordance with one embodiment of the invention, a method of processing interrupts, includes the following. An interrupt status message is transmitted after detecting a change in state...
6772258 Method and apparatus for sharing an interrupt between disk drive interfaces  
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry...
6772189 Method and system for balancing deferred procedure queues in multiprocessor computer systems  
A method and system for balancing deferred procedure queues in multiprocessor computer systems provides a greater use of multiprocessing power for the handling of hardware requests in a device...
6772259 Interrupt handlers used in different modes of operations  
According to the present invention, when an interrupt occurs in a computer system running an operating system, control takes a separate code path in the operating system, depending on whether the...
6766399 Application programming interface for temporary release of associated file locks on storage devices  
A method is provided for use in a computer system for performing an action on a storage volume being monitored by a program. The method includes the issuing of a command to suspend the...
6766400 Disk array apparatus and interrupt execution method of the same  
A disk array apparatus and an interrupt execution method of the same enables command processing received from an upper level apparatus to be executed in high-speed by reducing rate of the...
6766398 Method for processing PCI interrupt signals in a logically partitioned guest operating system  
The present invention generally provides embodiments relative to a method for PCI interrupt routing in a logically partitioned guest operating system. The method, which may be embodied upon a...
6760800 Event vector table override  
In an embodiment, a system may include a processor that handles a number of events. These events may include general purpose interrupts (GPIs) assigned to particular devices in the system....
6760783 Virtual interrupt mechanism  
A host coupled to a switched fabric including one or more fabric-attached I/O controllers. Such a host may comprise a processor; at least one host-fabric adapter coupled to said processor and...
6760799 Reduced networking interrupts  
An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a...
6757770 Computer system supporting a universal serial bus (USB) interface and method for controlling a USB corresponding I/O device  
A computer system and a method for controlling a USB FDD include a disk driver process routine including steps of requesting a disk drive process from a host program, if a subject of the disk...
6757771 Stack switching mechanism in a computer system  
A method and mechanism for performing an unconditional stack switch in a processor. A processor includes a processing unit coupled to a memory. The memory includes a plurality of stacks, a special...
6754738 Low overhead I/O interrupt  
An apparatus, method and program product for sending data to or receiving data from one or more I/O devices in an I/O operation with a main storage controlled by a processor in a data processing...
6754754 Apparatus and method for end of interrupt handling  
An interrupt vector is issued by an interrupt controller in response to an interrupt request. A processor executes an interrupt service routine in response to receiving the interrupt vector. Upon...
6754755 Service request system using an activity indicator to reduce processing overhead  
A service request system for a subsystem of a computer including a processor, a driver, and inhibit logic. The inhibit logic detects requests for service by the subsystem and asserts an interrupt...
6748472 Method and system for an interrupt accelerator that reduces the number of interrupts for a digital signal processor  
A circuit arrangement reduces the number of interrupts to a DSP required to transfer digital samples between external I/O devices and a data memory, thus allowing the DSP to perform additional...
6742089 Access controller and access method for controlling access from a CPU to a memory based on use states of plural access ports  
An access controller comprising plural access ports in which information associated with access from a CPU is stored for each access, and a bank management unit for managing use states of the...
6742065 Interrupt controller and method of accessing interrupts  
An interrupt controller and an interrupt handling method thereof are described. When there is an interrupt, a priority level of an interrupt source is determined and a corresponding branch...
6742093 Subsystem and method of reorganizing multiplexed data  
Disk units operable under control of different disk control units hold the same data. Under circumstances in which data is duplexed, when data is duplexed again after data that is generally saved...
6742060 Look-up table based circuitry for sharing an interrupt between disk drive interfaces  
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry...
6738846 Cooperative processing of tasks in a multi-threaded computing system  
Methods and apparatus for a cooperative processing of a task in a multi-threaded computing system are disclosed. In one aspect of the invention, a first thread is arranged to receive a task and...
6738848 Decoder-based circuitry for sharing an interrupt between disk drive interfaces  
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry...
6738847 Method for assigning a multiplicity of interrupt vectors in a symmetric multi-processor computing environment  
A method is disclosed for use in a multi-processor computer system having a multiplicity of peripherals coupled thereto. The disclosed method assigns interrupt vectors from the multiplicity of...
6734984 System having an arithmetic-logic circuit for determining the maximum or minimum of a plurality of codes  
A computer system or peripheral device includes an arithmetic-logic circuit that provides, for example, in binary parallel format a maximum code from a set of input codes, each input code in...
6725309 Multistage interrupt controller for receiving a plurality of interrupt signals to generate a priority interrupt signal  
A multistage interrupt controller provides a multistage storage means that processes external interrupt signals, including a plurality of multistage interrupt reception registers that can receive...
6721798 Method and apparatus for converting IP datagram to/from ethernet frames  
A method and apparatus is provided for an Ethernet station that transmits blocks of Ethernet frames in datagrams utilizing a pointer at the beginning of the datagram, rather than interrupts at the...
6721878 Low-latency interrupt handling during memory access delay periods in microprocessors  
A method and processor configured to handle an exception may employ a “retry” signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an...
6718414 Function modification in a write-protected operating system  
An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of...