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5809264 |
Interface with device having unusual access time and method thereof
An interface between a processor without ready or data acknowledge signal and a device having a remarkably slow or variable access time including: first and second latch terminals latching data and...
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5809559 |
System and method utilizing a virtual addressing buffer circuit to emulate a device which is physically not present
A method and apparatus using a virtual addressing buffer circuit afford address mapping and control flexibility to provide a unique opportunity for device emulation and software debugging. The...
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5809334 |
Receive packet pre-parsing by a DMA controller
A processor-based control system including a host processor, a data receiver device, a system memory, and an intelligent DMA controller. The DMA controller includes a pre-parsing section. The...
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5809309 |
Processing devices with look-ahead instruction systems and methods
A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the...
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5805901 |
Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system
A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests...
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5805906 |
Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions
In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to...
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5805883 |
Interrupt process distributing system
An interrupt process distributing system, provided in a CPU board in a loose-coupled type multiprocessor system formed of a plurality of CPU boards and one I/O board which are interconnected...
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5802345 |
Computer system with a reduced number of command end interrupts from auxiliary memory unit and method of reducing the number of command end interrupts
A computer system which includes a host machine having a memory and a CPU with an interrupt handling feature, an auxiliary memory unit for recording and reproducing data and an input/output unit...
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5802377 |
Method and apparatus for implementing multiple interrupt controllers in a multi-processor computer system
A method and apparatus for providing a distributed implementation of an interrupt delivery controller in a multi-processor environment while maintaining compliance with the OpenPIC specification....
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5802318 |
Universal serial bus keyboard system
A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion...
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5796996 |
Processor apparatus and its control method for controlling a processor having a CPU for executing an instruction according to a control program
In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer,...
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5797021 |
Information processing apparatus for emulation
An INTC and a CPU are interconnected via a bus. A first line through which an interrupt request signal is transferred to the CPU from the INTC, and a second line through which an interrupt...
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5790870 |
Bus error handler for PERR# and SERR# on dual PCI bus system
An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with...
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5790846 |
Interrupt vectoring for instruction address breakpoint facility in computer systems
An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more...
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5790871 |
System and method for testing and debugging a multiprocessing interrupt controller
A processing system comprising at least one processing unit, a plurality of I/O devices, and a central interrupt control unit intercoupling the processing unit and the plurality of I/O devices. The...
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5787290 |
Adapter with an onboard interrupt controller for controlling a computer system
A CHRP compliant Apple adapter is provided. The adapter comprises an onboard interrupt controller to control a peripheral component interconnect (PCI) based computer system. The adapter also...
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5784625 |
Method and apparatus for effecting a soft reset in a processor device without requiring a dedicated external pin
A system and method for emulating the state of a soft reset within a processor device without requiring a dedicated soft reset external pin associated with said processor device. The novel system...
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5784271 |
Data processor for interruption control between the CPU and the interruption controller
A data processor comprises a CPU and an interruption controller connected with control signal line. The CPU changes signal level at a control signal line in response to an interruption request. The...
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5778242 |
Software interrupt generator for computer bus interface
A computer peripheral interface solves the problem of the interrupt-line mismatch between the PCI and ISA bus architectures without requiring additional interrupt lines between ISA devices and the...
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5774377 |
Method and apparatus for monitoring a subsystem within a distributed system for providing an archive of events within a certain time of a trap condition
A method and apparatus for monitoring the behavior over time of a distributed system. Time-stamped data descriptive of events at one subsystem are placed into a local buffer. The subsystem is...
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5771387 |
Method and apparatus for interrupting a processor by a PCI peripheral across an hierarchy of PCI buses
A number of remote I/O ICUs, enhanced PCI--PCI bridges, and an ICC bus interface unit are distributively provided to a computer system having a processor and an hierarchy of PCI buses for...
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5768598 |
Method and apparatus for sharing hardward resources in a computer system
A method and apparatus for sharing a logic block between multiple peripheral/input/output I/O devices. A method and apparatus for generating a first interrupt in response to a request from one of...
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5768599 |
Interrupt managing system for real-time operating system
An interrupt managing system for a computer system in which resources are managed by a real-time operating system. The interrupt managing system has managed interrupt storage unit in which...
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5764997 |
System for generating interrupt requests from either side of an inter-chip bus
A method for generating an interrupt to a plurality of peripheral devices in a computer system, the computer system comprising a first bus, a bus bridge for coupling to the first bus and for...
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5764996 |
Method and apparatus for optimizing PCI interrupt binding and associated latency in extended/bridged PCI busses
An apparatus and method of implementing an enhanced PCI interrupt controller which accommodates the industry standard wire-or functionality. With such an arrangement a method and apparatus to...
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5764962 |
Emulation of asynchronous signals using a branch mechanism
A method facilitates transfer of control from normal emulation in an emulation system to an asynchronous signal handler in the emulation system. A branch-target register is globally allocated with...
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5764998 |
Method and system for implementing a distributed interrupt controller
A method and apparatus for providing a distributed implementation of an interrupt delivery controller in compliance with the OpenPIC specification. Specifically, a virtually unlimited number of...
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5765003 |
Interrupt controller optimized for power management in a computer system or subsystem
An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further...
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5764999 |
Enhanced system management mode with nesting
An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a...
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5761482 |
Emulation apparatus
An access condition coincidence detecting circuit detects that an address stored in an access condition storing register 44 is outputted to an address bus 29. When a counter 46 counts a certain...
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5761516 |
Single chip multiprocessor architecture with internal task switching synchronization bus
A plurality of processors which can be the same or different are formed on a single integrated circuit chip together with a memory controller and an I/O controller, and are interconnected by a data...
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5761427 |
Method and apparatus for updating host memory in an adapter to minimize host CPU overhead in servicing an interrupt
In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts...
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5761492 |
Method and apparatus for uniform and efficient handling of multiple precise events in a processor by including event commands in the instruction set
An integrated circuit having a digital processor, a decode stage for decoding an instruction from the instruction set, an execute stage coupled to the decode stage for executing the instruction,...
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5758168 |
Interrupt vectoring for optionally architected facilities in computer systems
An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more...
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5758169 |
Protocol for interrupt bus arbitration in a multi-processor system
A multi-processor system includes an interrupt bus used for arbitrating among eligible processors to determine which processor is to service of an interrupt request. The interrupt bus comprises...
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5758190 |
Control unit threshold timeout controls for software missing interrupt handlers in operating systems
I/O control unit (CU) features for supporting multiple host operating systems (OSs) which use missing interrupt handler (MIH) timeout functions for detecting potential failures of requested I/O...
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5758167 |
Interrupt management unit and a method for identifying an interrupt request having the highest priority
A management unit for microcontrollers equipped with a decoder for a plurality of interrupt channels, the unit being connected to a central processing unit of the microcontroller to decode and...
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5754866 |
Delayed interrupts with a FIFO in an improved input/output architecture
Apparatus for transferring commands over a system transmission path between first and second components in a digital data system including a first-in first-out circuit having a plurality of stages...
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5754889 |
Auto write counter for controlling a multi-sector write operation in a disk drive controller
A host interface uses a state machine to control multiple sector transfers between a host computer and a physical storage medium, so that the idle time between sector transfers is minimized and not...
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5748970 |
Interrupt control device for processing interrupt request signals that are greater than interrupt level signals
An interrupt control device of an embedded microcomputer including I/O devices and a processor core comprising: a program storage unit for storing interrupt processing programs, each corresponding...
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5748971 |
Option card hibernation system
A hibernation system of a computer employing option cards responds to a hibernation interrupt signal generated by a power management system in case of power failure or a period of non-use. In...
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5745770 |
Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor
A microprocessor includes the capability to service at least one debug exception and an I/O trap generated during execution of a single instruction. After executing each instruction, the...
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5745771 |
Disc array device and disc control method
A plurality of disc units, an array control unit, and a host controller connecting mechanism for connecting them to a host controller through a system interface are mounted on the same circuit...
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5745763 |
Method and apparatus for device driver funnelling
A method and apparatus for enabling AIX device driver (DD) created for a uniprocessor (UP) system to run unchanged on a symmetrical multiprocessor system (SMP). Device drivers are processed by a...
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5740467 |
Apparatus and method for controlling interrupts to a host during data transfer between the host and an adapter
An apparatus and method for transferring data in a data processing system to and from a host system. A communication adapter or input/output controller device is provided in which queues are...
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5740450 |
Method to automatically detect the interrupt channel status of an add-on card
A method to automatically detect the interrupt channel status of an add-on card by providing an IRQ set port, an IRQ status port, and an IRQ force port on the card wherein the IRQ set port is used...
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5740449 |
Method and apparatus for managing interrupts in a data processing system
A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the...
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5740451 |
Microcomputer having function of measuring maximum interrupt-disabled time period
A microcomputer comprises a timer controller for detecting a time when a disabled state in which interrupts are disabled starts and a time when the disabled state ends, a count timer which starts a...
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5737545 |
Computer bus mastery system and method having a lock mechanism
A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished...
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5734911 |
Method of linking peripheral devices all of which use the same IRQ to a single interrupt procedure
A method of linking peripheral devices to a single interrupt procedure in a computer is comprised of storing in an interrupt vector table of a BIOS ROM, a first pointer to an interrupt service...
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