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6981083 Processor virtualization mechanism via an enhanced restoration of hard architected states  
A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the...
6981084 Apparatus and method for packet ingress interrupt moderation  
A method and apparatus for moderating packet ingress interrupts. A network interface includes a packet timer and an absolute timer or absolute counter. The packet timer functions to minimize...
6981079 Critical datapath error handling in a multiprocessor architecture  
A interrupt is generated for all processors in a multiprocessor system when a critical datapath experiences an error. Serialization code in the interrupt handling routine for that interrupt...
6981178 Separation of debug windows by IDS bit  
A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The...
6976110 Method and apparatus for reducing interrupt latency by dynamic buffer sizing  
A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is...
6973583 Information processing apparatus having an interrupt function  
The present invention aims to reduce a waiting time of an information processing machine from reception of an interrupt request signal to an actual start of an interrupt process. The information...
6967950 Pull transfers and transfer receipt confirmation in a datapipe routing bridge  
In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal...
6968411 Interrupt processing apparatus, system, and method  
An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, implement interrupt processing in an efficient, parallel...
6968410 Multi-threaded processing of system management interrupts  
An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected...
6963970 System and method for executing a fast reset of a computer system  
A system and method for implementing a fast reset of a computer system is described. In one implementation, the fast reset is implemented by adding a new ResetType to the EFIResetSystem( )...
6959262 Diagnostic monitor for use with an operating system and methods therefor  
A computer-implemented method for monitoring a computer system when the computer system executes a user application using a production operating system (OS) is disclosed. The method includes...
6954922 Method apparatus and article of manufacture for time profiling multi-threaded programs  
Methods, systems, and articles of manufacture consistent with the present invention time profile program threads using data corresponding to states of the registers of a processor(s) executing the...
6952749 Multiprocessor interrupt handling system and method  
An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the...
6944746 RISC processor supporting one or more uninterruptible co-processors  
A system and method for processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor. Instructions are processed in the processor...
6941424 System, method, and computer program product for high speed DMA-based backplane messaging  
A system and method of enhanced backplane messaging among a plurality of computer boards communicating over a common bus uses a set of pre-allocated buffers on each computer board to receive...
6941398 Processing method, chip set and controller for supporting message signaled interrupt  
A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in...
6938115 Method and computer device with different criticality  
A computer system and method are provided for executing multiple software of different mission-criticality. The computer system includes at least one access control circuit to prevent access to...
6934783 Method for the scheduled execution of a target function  
A method for the scheduled execution of program steps (target function) by the processor of a computer at predetermined times, in which a register of the computer is read repeatedly and this value...
6934784 Systems and methods for managing-system-management-event data  
A method and system for system-management event detection, consolidation, reporting and storage is provided. The method and system may be used in a computer system for above-mentioned purposes....
6934738 Message processing apparatus  
A message processing apparatus which handles messages exchanged over a network and explicitly notifies the recipient of the importance and other information regarding each received message....
6931643 Interrupt throttling for inter-processor communications  
Implementation of communication between data processors includes a first task (A) running on a first data processor (11) determining that communication is desired between the first task and a...
6928502 Method and apparatus for processing interrupts at dynamically selectable prioritization levels  
A method and apparatus are described by which interrupts from a source may be processed at a dynamically selectable level of priority. A system that has at least two different interrupt request...
6922746 Data processing system preventing configuration cycles to permit control procedure selection for access to attached devices  
In one embodiment of the present invention, a process that uses a first processor is provided. The process includes the operation of blocking by the first processor of completion by a second...
6907485 Hybrid change of state protocol for CANOpen networks  
A CANOpen network including a bus master and an I/O module are disclosed. Each are communicatively coupled to a common bus. The I/O module is subject to a state change. The bus master collects...
6907521 Enabling video BIOS and display drivers to leverage system BIOS platform abstract  
A method for enabling communication between system BIOS and a graphics device is described herein. In one embodiment, a graphic device sets a system management interrupt (SMI) bit in an interface...
6901475 Link bus for a hub based computer architecture  
A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a...
6898651 Method, apparatus, and system for generating serial interrupt requests (IRQ) with power savings  
According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one...
6898262 Programmable controller  
An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle...
6895448 Low-power audio CD player for portable computers  
A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the...
6895003 Communication system, apparatus, and method in which data transmission is interrupted for a bus reset  
A communication system, in which data transmission is interrupted for a bus reset, includes a source and a destination with a receiving buffer. The source is adapted to transmit a segment of data...
6892260 Interrupt processing in a data processing system  
The present invention relates generally to interrupt processing. One embodiment relates to a method for executing an interrupt in a data processing system including fetching a conditional store...
6892261 Multiple operating system control method  
An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one...
6889167 Diagnostic exerciser and methods therefor  
A computer-implemented method for diagnosing the performance of a computer system using a diagnostic application. The method includes providing a diagnostic application and providing an operating...
6889279 Pre-stored vector interrupt handling system and method  
A pre-stored vector interrupt handling system for rapidly processing interrupt requests from input/output (I/O) devices in processor-based systems includes selection logic and an interrupt vector...
6883053 Data transfer control circuit with interrupt status register  
A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined...
6880021 Intelligent interrupt with hypervisor collaboration  
An apparatus, method and program product for controlling the transfer of data in a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by...
6880029 Programmable controller  
In a programmable controller which executes a user program process, an I/O refresh process and a peripheral service process by using a same microprocessor, the cyclic execution of the peripheral...
6874049 Semaphores with interrupt mechanism  
Disclosed is a multiprocessor system including a semaphore register and a semaphore interrupt register. In addition, for each processor in the multiprocessor system, there is a semaphore interrupt...
6865636 Multitasking processor system for monitoring interrupt events  
In a processor system, different memory means (8), which can in each case comprise a memory stack (9) for the instruction counter, a register (10) for temporarily storing data and status register...
6862641 Interruptable and re-enterable system management mode programming code  
Interruptable and re-enterable system management mode (SMM) programming code. The code includes one or more instructions, an entry or exit location, and one or more instructions. The code is...
6859845 System for resolving conflicts due to simultaneous media streams and method thereof  
A system and methods are provided for resolving resource conflicts related to processing multiple media streams on a single media device. An audio/video (A/V) server is used to interconnect a...
6857064 Method and apparatus for processing events in a multithreaded processor  
In a multithreaded processor, events are categorized according to which of a “soft” state clearing (“nuke”) process and a “hard” nuke process should be performed in response to each event. When an...
6851006 Interruption handler-operating system dialog for operating system handling of hardware interruptions  
Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for...
6836881 Remote tracing of data processing nodes in an asynchronous messaging network  
Remote tracing from a local data processing node of the execution of a process within an application program running on a remote data processing node in a distributed data processing network. The...
6834352 Method and apparatus for maximizing an advertising effect using a control unit to detect if advertisement is being displayed and suspending a function if advertisement is not displayed  
A computer includes a central processing unit (CPU), a memory, an input unit, a monitor, an advertisement presenting program for presenting an advertisement on the monitor, and a controlling unit...
6823460 Method and system for intercepting an application program interface  
A method of intercepting application program interface, including dynamic installation of associated software, within the user portion of an operating system. An API interception control server in...
6823467 Method and apparatus for arbitrary resolution interval timeouts  
Methods and apparatus for enabling timeouts with arbitrary resolutions to be implemented are disclosed. According to one aspect of the present invention, a method for enabling a device driver to...
6823414 Interrupt disabling apparatus, system, and method  
An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities...
6823413 Interrupt signal processing apparatus  
An interrupt signal processing apparatus, when receiving an interrupt requesting signal from one device, writes a pulse signal generated by an interrupt setting pulse generating section to a...
6820153 Interrupt processing and memory management method in an operation processing device and a device using the same  
In operation processing devices based on Java (a registered trademark), each time a functional program is executed, in response to a command to access that function, a work area for the program...