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5933648 |
Configurable arbitration device for controlling the access of components to an arbiter or the like based on a control input
A number, Y, of ports are coupled to a common bus and to a bus arbitration extension device. The extension device is coupled to X pairs of arbitration signal lines, where X is less than Y. The...
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5925115 |
Method and system for extending interrupt sources and implementing hardware based and software based prioritization of interrupts for an embedded processor
The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt...
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5923887 |
Interrupt request that defines resource usage
An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a...
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5920258 |
Alarm signal processing circuit
An alarm signal processing circuit is provided for an integrated circuit having alarm signal generating circuitry for generating alarm signals having active and inactive states, and for connecting...
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5918056 |
Segmentation suspend mode for real-time interrupt support
A device and method that suspends segmentation addressing and prevents the modification of segmentation information (the segment registers and segment descriptors). By suspending segmentation...
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5918057 |
Method and apparatus for dispatching multiple interrupt requests simultaneously
An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one...
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5911040 |
AC checkpoint restart type fault tolerant computer system
A checkpoint restart type computer system which executes a program upon taking a checkpoint periodically for rolling back to a prior checkpoint if an error status is detected during an execution of...
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5905897 |
Method and apparatus for selecting a nonblocked interrupt request
An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one...
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5898877 |
Processor using special instruction set to enhance exception handling
A processor uses a special instruction set to enhance exception handling, such as interrupt handling. The processor uses a pipeline comprising five separate stages of fetch, decode, execute, memory...
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5898859 |
Address shadow feature and methods of using the same
An address shadow feature and methods of using the same. A slave controller of the present invention includes an address register coupled to receive a device address from a secondary bus interface....
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5898878 |
Data processing system having capability to interpolate processing coefficients
A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the...
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5896540 |
Method and apparatus for controlling data transfer between a host and a peripheral in a pre-reading mode, post-reading mode and both-reading mode
The object is to control an interrupt request to be asserted to a host in all of a prereading mode, a postreading mode, and a both-reading mode. Until the count value of a counter becomes equal to...
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5894577 |
Interrupt controller with external in-service indication for power management within a computer system
An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further...
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5894587 |
Multiple bus bridge system for maintaining a complete order by delaying servicing interrupts while posting write requests
A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts...
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5894583 |
Variable timeout method for improving missing-interrupt-handler operations in an environment having I/O devices shared by one or more systems
Missing interrupt handler (MIH) software features for supporting a variable MIH timeout for I/O requests issued by an operating system (OS). The MIH timeout is varied to prevent a false indication...
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5892956 |
Serial bus for transmitting interrupt information in a multiprocessing system
A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line...
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5892957 |
Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system
An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input...
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5889978 |
Emulation of interrupt control mechanism in a multiprocessor system
A multiprocessor computer system that includes an emulation feature for lowest priority processor software compatibility while providing fault tolerance includes first and second processors coupled...
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5889973 |
Method and apparatus for selectively controlling interrupt latency in a data processing system
Method and apparatus for selectively controlling interrupt latency in a data processing system (10). In one embodiment, the present invention uses an interrupt control register bit field (50) to...
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5890002 |
System and method for bus master emulation
A system and method in accordance with the invention allows the emulation of a DMA transfer between a device such as a CD-ROM which is incapable of a bus-mastering mode of operation (e.g., a DMA...
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5887175 |
Apparatus and method for managing interrupt delay on floating point error
A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is set, interrupts are to be handled. However, if the IF flag...
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5881294 |
System for transforming PCI level interrupts
A system for transforming computer system interrupts from state based interrupts to event based interrupts. The system of the present invention includes an interrupt acknowledge detection circuit...
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5875341 |
Method for managing interrupt signals in a real-time computer system
A method for the operation of a computer system controlled by a real-time operating system, which computer system processes interrupt signals. Upon the occurrence of an interrupt signal, the...
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5872982 |
Reducing the elapsed time period between an interrupt acknowledge and an interrupt vector
In general, in one aspect, the invention features a method for reducing the elapsed period between the time an interrupt acknowledge is issued by a CPU and the time when the corresponding interrupt...
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5870623 |
I/O port for determining accidents in an external device
A port logical level detection circuit ((81)) detects whether a voltage level of a port (15a) is high or low with respect to a plurality of threshold values. A comparison circuit (82) compares a...
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5870612 |
Method and apparatus for condensed history buffer
The invention includes a method and apparatus for maintaining content of predefined registers of a processor which uses the registers for executing instructions, including an interruptible...
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5862388 |
Interrupt-time processing of received signals
A computer system with an operating system and a data-processing system running on a host processor, and a receiver. The receiver sends interrupt signals to the operating system after the receiver...
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5862308 |
Fault intercept and resolution process independent of operating system
A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling module includes the steps of: setting an...
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5862366 |
System and method for simulating a multiprocessor environment for testing a multiprocessing interrupt controller
A multiprocessing system comprising a plurality of processors and a plurality of I/O devices. A central interrupt control unit functionally intercouples the plurality of processors and I/O devices....
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5860014 |
Method and apparatus for improved recovery of processor state using history buffer
A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in...
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5860013 |
Flexible interrupt system for an integrated circuit
A flexible interrupt system for presenting interrupt signal to a microcontroller located on an integrated circuit responds to either on chip or off chip components. An interrupt circuit is...
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5857108 |
Device and method for generating interrupts
A device and method for generating an interrupt for a microcontroller (MCU) are disclosed. The device includes a first storing circuit for storing signals received/transmitted through a plurality...
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5852729 |
Code segment replacement apparatus and real time signal processor using same
A sequence of instructions for a processor executing a plurality of real time programs is supplied from a memory having a set of memory locations. A controller is coupled to the memory for...
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5850521 |
Apparatus and method for interprocessor communication
In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored...
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5850555 |
System and method for validating interrupts before presentation to a CPU
A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity...
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5848278 |
Serial interrrupt control system in a system in which a plurality of interrupt requesters are connected to a serial bus
In an interrupt control system to be applied, especially, to a laptop or notebook type personal computer that can use an expansion unit, an interrupt encoder converts the leading edges of a...
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5848277 |
Method for providing both level-sensitive and edge-sensitive interrupt signals on a serial interface between a peripheral and host
A method or protocol for generating an Interrupt Signal for communication between a peripheral device and a host processor having either a level-sensitive or an edge-sensitive interrupt detector....
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5845131 |
Multiprocessor system employing an improved self-coded distributed interrupt arbitration technique
A multiprocessor system has a shared bus and a plurality of processor modules, wherein the shared bus includes an interrupt bus and each of the processor module contains an interrupt controller....
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5845133 |
Virtualized functions within a microprocessor
A system and method for virtualizing external pins and their internal functions within a microprocessor employing an operating system independent interrupt and N subhandlers to virtual the...
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5842078 |
Apparatus for generating an interrupt by comparing newly received, preceding stored, and optional data where designated storing areas have a plurality of switching
An interface apparatus, built in a microcomputer, and capable of reducing the load on a CPIU by including a function to judge by itself, when data is received from the outside, whether it is...
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5842026 |
Interrupt transfer management process and system for a multi-processor environment
An interrupt mechanism handles an interrupt transaction between a source processor and a target processor on separate nodes in a multi-processor system. The nodes are connected to a network through...
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5832492 |
Method of scheduling interrupts to the linked lists of transfer descriptors scheduled at intervals on a serial bus
A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures...
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5832202 |
Exception recovery in a data processing system
A processing device performs operations in response to program instructions. In particular, values are written to a data memory of the system, which alters a defined visible state of the system. In...
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5828890 |
System for interrupting program operation when an out-of-range value is encountered to correct a data value
System for suspending operation of a program after detecting that an instruction is executing with an operand assuming an out-of-range value such as a year value out of the range of the program....
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5826091 |
Method and apparatus for regenerating edge-sensitive interrupts
The interrupt regenerator circuit converts the transition signal caused by a passenger's data entry in an aircraft entertainment system into a triggering signal. The triggering signal triggers a...
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5819096 |
PCI to ISA interrupt protocol converter and selection mechanism
An interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCI agent interrupts are processed by programmable...
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5819095 |
Method and apparatus for allowing an interrupt controller on an adapter to control a computer system
A method and apparatus of making a computer system using the peripheral component interconnect (PCI) bus architecture compatible with an Apple computer system are provided. In a preferred...
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5815702 |
Method and software products for continued application execution after generation of fatal exceptions
A method of operating a computer and a software product, enable a computer system and application to continue execution after the application has generated a fatal exception. This allows the user...
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5812858 |
Method and apparatus for providing register and interrupt compatibility between non-identical integrated circuits
An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for...
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5812796 |
Support structures for an intelligent low power serial bus
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a...
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