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6038632 |
Interrupt control on SMM
In an initialization operation of a system, an I/O trap SMI is issued to a CPU, and CPU state map information is stored in a predetermined area in an SM-RAM. When an interrupt control process...
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6032245 |
Method and system for interrupt handling in a multi-processor computer system executing speculative instruction threads
In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being...
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6031973 |
Robot and its controller method
A robot controller and its control method use a generic personal computer and a PC operating system. The controller 10 comprises the following: a task-switching unit 30 that switches tasks on a...
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6032213 |
PC core logic chipset comprising a serial register access bus
A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first...
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6029222 |
Method and processor for selectively marking instructions as interruptible or uninterruptible and judging interrupt requests based on the marked instruction
Each of microcodes 1 has an interrupt prohibit bit 10 that specifies acceptance or nonacceptance of an interrupt request. Upon occurrence of an interrupt request, a processor refers to a value set...
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6023740 |
Handling interrupts in a synchronous environment
The invention relates to a method and system by means of which a large number of peripheral modules (TRn) can request service from a controller, e.g. in form of an interrupt request. Congestion of...
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6021457 |
Method and an apparatus for minimizing perturbation while monitoring parallel applications
A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes...
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6021456 |
Method for communicating interrupt data structure in a multi-processor computer system
A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge...
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6018785 |
Interrupt-generating hardware semaphore
The hardware semaphore generates an interrupt signal upon a change in ownership status of a shared resource. In particular, the semaphore apparatus generates an interrupt signal when a requesting...
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6016531 |
Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller
A system for managing the flow of real time data streams into a data system cache memory is disclosed. The data system includes a central processing unit or micro controller, with a cache memory,...
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6016548 |
Apparatus for controlling duty ratio of power saving of CPU
A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a...
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6012081 |
Service and event synchronous/asynchronous manager
A service and event synchronous/asynchronous manager (SESAM) which provides a programmer interface to concurrency, dispatching and synchronization in an object oriented computing system. SESAM...
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6012121 |
Apparatus for flexible control of interrupts in multiprocessor systems
An apparatus for a distributed system having a plurality of nodes and a switch network for passing messages between nodes, each message being sent from a source node to a target node. Each node is...
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6005674 |
System architecture for multiple input/output devices
A system or a board that interacts with a processor and multi I/O devices such as high-speed facsimile modems. The processor inputs/outputs data to I/O devices. Each I/O device includes an...
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6006301 |
Multi-delivery scheme interrupt router
An interrupt router includes a first interface. The first interface is coupled to a first interrupt delivery medium. The interrupt router includes a second interface. The second interface is...
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6000002 |
Protection circuit for program-controlled electrical equipment
A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt...
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5999993 |
Data transfer system having function of preventing error caused by suspension of data transfer to immediately service transfer interrupted request
A data transfer system including a data transmission unit and a data reception unit, the data transmission unit including an arithmetic unit which, when accepting an interruption during data...
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5995743 |
Method and system for interrupt handling during emulation in a data processing system
A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method,...
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5991790 |
Generation and delivery of signals in a two-level, multithreaded system
A system for properly delivering an signals in a computer system. A first module is called which waits for a signal to be generated. Upon a signal being generated, the first module is notified of...
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5987556 |
Data processing device having accelerator for digital signal processing
A data processing device uses a processor such as a central processing unit and a special-purpose hardware circuit, such as an accelerator for accelerating the software operation using the...
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5987495 |
Method and apparatus for fully restoring a program context following an interrupt
A method and apparatus for fully restoring the context of a user program, including program status word (PSW) and CPU register contents, following an asynchronous interrupt. Upon the occurrence of...
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5987537 |
Function selector with external hard wired button array on computer chassis that generates interrupt to system processor
The invention is a computer system with a button array on the computer chassis for simulating the operation of common consumer electronic devices. Each button of the array of buttons is hardwired...
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5987538 |
Apparatus for initiating generation of an inter-processor interrupt by a peripheral device not directly connected to any of the multi-processor local interrupt controllers
Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer...
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5987554 |
Method of controlling the transfer of information across an interface between two buses
A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a...
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5987258 |
Register reservation method for fast context switching in microprocessors
Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler...
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5983275 |
Apparatus for and method of providing interrupts to a host processor in a frame receiving system
In an interrupt-driven data frame stream receiver, an interrupt to a host processor is applied by an interrupt system that comprises a timer logic circuit, an address match circuit, a data frame...
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5978860 |
System and method for disabling and re-enabling at least one peripheral device in a computer system by masking a device-configuration-space-access-signal with a disable or re-enable signal
A system and method for disabling and re-enabling peripheral devices (PDs) in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a...
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5978865 |
System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted
A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which...
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5978910 |
Performing pending interrupts or exceptions when interruptible jumps are detected
A circuit for processing a jump operation also enables handling pending interrupts or exceptions. The jump operation has an operand specifying a destination address. If an interrupt or exception is...
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5974261 |
Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability
A computer system has a processing unit with suspend/resume capability, a memory, and a hard disk drive. In response to a first command from the processor, the hard disk drive sends its status to...
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5968159 |
Interrupt system with fast response time
The present invention is related to a data handling system comprising a central processing unit for executing a sequence of commands stored in a memory. This central processing unit comprises an...
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5966529 |
Processor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct execution
A processor having a virtually addressable primary operand register file (PORF) is further provided with an auxiliary operand register file (AORF) to facilitate non-disruptive adjunct Execution....
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5966543 |
Method of using collaborative spinlocks to provide exclusive access to a resource in a multiprocessor computer system
A multiprocessor computing system has memory shared by all processors of the computing system and includes an symmetric multiprocessor (SMP) operating system and at least one external device...
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5961585 |
Real time architecture for computer system
A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To...
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5963737 |
Interupt vectoring for trace exception facility in computer systems
An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application...
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5958036 |
Circuit for arbitrating interrupts with programmable priority levels
Apparatus for arbitrating the selection of an interrupt for servicing from a plurality of interrupts in which a priority level for each of the plurality of interrupts is programmed in a first...
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5956511 |
Program development support apparatus, program development support method, and storage medium therefor
A program development support apparatus and method for supporting the efficient development of a highly reliable program are provided. The basic configuration includes a program-outputting which...
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5953535 |
Using intelligent bus bridges with pico-code to service interrupts and improve interrupt response
A computer system having an improved method of handling interrupts associated with I/O operations to reduce interrupt latencies. The computer system includes one or more processing units, a memory...
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5951669 |
Method and apparatus for serialized interrupt transmission
A computer system in which interrupt signals are serially transmitted from an input/output (I/O) controller is disclosed. The I/O controller initially receives the interrupt signals and then...
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5951676 |
Apparatus and method for direct loading of offset register during pointer load operation
An apparatus and method for loading a pointer into a selector register/general purpose register pair is provided. The apparatus and method utilizes a single micro instruction to load an offset...
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5944809 |
Method and apparatus for distributing interrupts in a symmetric multiprocessor system
A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable...
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5941976 |
Interrupt request deassertion interlock mechanism
An interrupt circuit on a first integrated circuit receives a plurality of interrupt request signals, at least one of which is provided over a bus. A interrupt synchronization control circuit...
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5943506 |
System for facilitating data I/O between serial bus input device and non-serial bus cognition application by generating alternate interrupt and shutting off interrupt triggering activities
A system management interrupt (SMI) generation circuitry is provided to a universal serial bus (USB) complaint personal computer (PC) for generating a SMI whenever the USB controller attempts to...
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5943479 |
Method for reducing the rate of interrupts in a high speed I/O controller
A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is...
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5943507 |
Interrupt routing circuits, systems and methods
A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ("MPU" 102), a peripheral...
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5938742 |
Method for configuring an intelligent low power serial bus
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a...
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5938758 |
Microprocessor having function of prefetching instruction
A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first...
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5931937 |
Symmetric parallel multi-processing bus architecture
An apparatus for and method of coupling a number of data processing components onto a bus for communication amongst the components with a symmetric parallel multi-processing bus system...
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5931934 |
Method and apparatus for providing fast interrupt response using a ghost instruction
A data processing device 100 uses a portion of a random access memory 111 as an input buffer for holding a portion of a stream of data which is received by an input interface 130. Likewise, a...
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5931935 |
File system primitive allowing reprocessing of I/O requests by multiple drivers in a layered driver I/O system
I/O systems of computers typically utilize multiple layered drivers to process I/O requests. I/O requests are passed from one driver to another in a defined sequence with each driver performing its...
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