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7089341 Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platform  
Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform). One...
7086058 Method and apparatus to eliminate processor core hot spots  
Methods and apparatus are provided for eliminating hot spots on processor chips in a symmetric multiprocessor (SMP) computer system. Some operations, in particular, floating point multiply/add,...
7082486 Method and apparatus for counting interrupts by type  
A method, apparatus, and computer instructions for counting interrupts by type. An interrupt count is incremented when a particular type of interrupt occurs. The count may be stored in the IDT or...
7080188 Method and system for embedded disk controllers  
A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a...
7073006 Implementing hardware interrupt event driven mechanism to offer soft real-time universal serial bus  
A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the...
7069367 Method and apparatus for avoiding race condition with edge-triggered interrupts  
An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an...
7065598 Method, system, and article of manufacture for adjusting interrupt levels  
Provided are a method, system and article of manufacture for adjusting interrupt levels. A current system interrupt rate at a computational device is determined, wherein the current system...
7065597 Method and apparatus for in-band signaling of runtime general purpose events  
A method and apparatus for communicating general purpose events in-band from a downstream controller is presented.
7062766 Embedded system with interrupt handler for multiple operating systems  
A communication device includes one processor to run at least two operating systems simultaneously. The at least two operating systems include a first operating system for mobile station functions...
7058743 Method and device for dynamic interrupt target selection  
A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation...
7058799 Apparatus and method for clock domain crossing with integrated decode  
An apparatus and method for transferring signals between timing domains. The apparatus includes a receiver for receiving signals operative in a first timing domain, a decoder for at least...
7054974 System for end of interrupt handling  
An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector...
7054975 Interrupt generation in a bus system  
The present invention relates to a bus system comprising a first and second station (10, 14) coupled via a bus (12) for transferring data and control signals, the bus (12) operating according to a...
7054973 Computer system with collapsible keyboard and alternate display functions and processing method thereof  
A computer system with collapsible keyboard and alternate display functions. The computer system includes a main body which stores at least one application. A monitor and collapsible keyboard are...
7054958 Apparatus and method for responding to a interruption of a packet flow to a high level data link controller in a signal processing system  
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the...
7054972 Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system  
An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO...
7054982 Fieldbus interface board  
An apparatus and method including a fieldbus interface board connected to a fieldbus line. The fieldbus interface board includes a main control unit controlling an overall operation of the board....
7051177 Method for measuring memory latency in a hierarchical memory system  
A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads...
7048877 Efficiently supporting interrupts  
A method, system, and article of manufacture to efficiently support interrupts of a computer system. A message-based interrupt from a device of the computer system is intercepted. A fake...
7051137 Event delivery  
Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may...
7051138 Interrupt-processing system for shortening interrupt latency in microprocessor  
The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both...
7051146 Data processing systems including high performance buses and interfaces, and associated communication methods  
A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one...
7047372 Managing I/O accesses in multiprocessor systems  
A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is...
7043589 Bus system and bus interface  
The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a...
7043587 System and method for connecting a universal serial bus device to a host computer system  
A method and system for controlling the addition of a USB device to a host computer system via a hardware hot plug detector that monitors USB ports. The differential signal lines connecting to the...
7043583 Method and system for improved processing of CPU intensive communications protocols  
A method of processing a frame of a CPU intensive communications protocol includes disabling per frame interrupts of a CPU; enabling a periodic interrupt handler to interrupt the CPU upon an...
7043729 Reducing interrupt latency while polling  
Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system...
7043582 Self-nesting interrupts  
A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may...
7039738 Method and system for handling device driver interrupts  
A method and system for handling device driver interrupts in a computer system. An interrupt handling Method is initiating prior to the occurrence of any interrupts in the computer system. The...
7032049 Apparatus for relaying received interrupt requests  
An apparatus is described which is distinguished by the fact that the apparatus does not output an interrupt request until after a plurality of interrupt requests have been received. The apparatus...
7028122 System and method for processing node interrupt status in a network  
The invention relates to the processing of state information such as interrupt status in a hierarchical network of nodes having a tree configuration. There is a root node at the top of the...
7028123 Microcomputer, has selection circuit to select either testing-purpose interrupt request signal or interrupt request selection signal based on delayed selection signal, where selected signals are sent to interrupt controller  
In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request...
7024509 Passive release avoidance technique  
A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of...
7016997 Method for determining an interruption source  
A testing method to discern an original source with respect to the interruption, suitable for use in a computer system is provided. The computer system includes an integrated drive electronics...
7016998 System and method for generating sequences and global interrupts in a cluster of nodes  
A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed...
7013358 System for signaling serialized interrupts using message signaled interrupts  
The present invention provides a system for signaling legacy serialized interrupts within a PCI-Express environment, using message signaled interrupts. The system provides structures and methods...
7003700 Halting execution of duplexed commands  
A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the...
7003615 Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device  
An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of...
7003611 Method and apparatus for handling interrupts using a set of interrupts servers associated with presentation controllers  
A method, apparatus, and computer instructions for managing interrupts using a set of presentation controllers. A first interrupt server is identified in the set of interrupt servers to handle the...
7003610 System and method for handling shared resource writes arriving via non-maskable interrupts (NMI) in single thread non-mission critical systems with limited memory space  
A system and method for handling shared resource writes arriving via non-maskable interrupts in single thread non-mission critical system with limited memory space includes a queue for providing...
7000059 Integrated PCI interface card and bus system thereof  
The present invention discloses an integrated PCI interface card and the bus system thereof. The integrated PCI interface card of the present invention includes at least two bus masters, a control...
7000058 Method and configuration for transmitting digital data  
A method for transmitting digital data, which is continued in data frames of variable lengths, from a first data bus to a second data bus, which is operated asynchronously with respect to the...
6996705 Method and system for configuring the language of the BIOS in a computer system  
The present invention comprises a method and system for configuring the language of a BIOS of a computer system. The method and system comprise providing a plurality of BIOS images in the computer...
6993613 Methods and apparatus for reducing receive interrupts via paced ingress indication  
Methods, apparatus, and articles of manufacture for efficiently handling incoming network traffic by preventing protocol stack overruns and minimizing packet latency are disclosed herein....
6988155 Aggregation of hardware events in multi-node systems  
The aggregation of hardware events in multi-node systems is disclosed. An event occurring at a remote node is forwarded to a primary node, by firmware of the remote node writing to a first...
6988156 System and method for dynamically tuning interrupt coalescing parameters  
A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many...
6985986 Variable cycle interrupt disabling  
A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to...
6986136 Web-based imaging service enabling jobs to be interrupted gracefully  
In a web-based imaging environment, a user accesses a destination service (e.g., representing a printer), which retrieves user's imaging data and configures available production options for a...
6986031 Device and method for processing a control action from a user  
A device for processing a control action from a user in an electronic apparatus including a controller and a detection circuit. The controller outputs a voltage signal having a voltage deviation...
6983339 Method and apparatus for processing interrupts of a bus  
A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an...