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6154832 |
Processor employing multiple register sets to eliminate interrupts
A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other...
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6151664 |
Programmable SRAM and DRAM cache interface with preset access priorities
A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on...
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6148361 |
Interrupt architecture for a non-uniform memory access (NUMA) data processing system
A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The...
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6148360 |
Nonvolatile writeable memory with program suspend command
A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control...
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6145030 |
System for managing input/output address accesses at a bridge/memory controller
An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O...
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6145047 |
Circuit and method for converting interrupt signals from level trigger mode to edge trigger mode
Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge...
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6145007 |
Interprocessor communication circuitry and methods
A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a...
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6131137 |
Drive control unit and optical memory apparatus
An optical memory apparatus, in which an ODC section generates an interruption according to an instruction from an upper system, an ODD section provides drive controls over a memory apparatus...
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6128691 |
Apparatus and method for transporting interrupts from secondary PCI busses to a compatibility PCI bus
During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication...
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6125236 |
Method and apparatus for providing user control of multimedia parameters
A computer system for providing user control of multimedia output parameters. The computer system includes a central processing unit (CPU) coupled to a memory unit. The memory unit includes a...
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6125456 |
Microcomputer with self-diagnostic unit
To perform the self-diagnostic of the CPU, the CPU monitor macro service is activated in response to the interrupt signal from the external. In the CPU monitor macro service, according to the CPU...
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6125443 |
Interrupt processing system and method for information processing system of pipeline control type
An interrupt processing system and method for an information processing system of pipeline control type are disclosed. The occurrence of an exception is detected for each plurality of instructions...
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6122700 |
Apparatus and method for reducing interrupt density in computer systems by storing one or more interrupt events received at a first device in a memory and issuing an interrupt upon occurrence of a first predefined event
A method and apparatus for reducing interrupt density in a computer system. One or more interrupt events received at a first device are stored in a memory and an interrupt is issued from the first...
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6122679 |
Master DMA controller with re-map engine for only spawning programming cycles to slave DMA controllers which do not match current programming cycle
A computer system implementing a distributed direct memory access architecture is disclosed. The computer system includes a re-map engine that includes control logic and a shadow register for each...
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6122701 |
Device volume control in multimode computer systems
A volume control handler allows users to dynamically alter the volume level of an audio device when the device is under control of a DOS mode application. The dynamic volume adjustment is performed...
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6115777 |
LOADRS instruction and asynchronous context switch
A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a...
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6115780 |
Interrupt steering circuit for PCI bus
In an interrupt steering circuit for a computer system having a PCI bus connected to four expansion slots, a controller includes a non-volatile memory previously storing a selection information of...
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6115776 |
Network and adaptor with time-based and packet number based interrupt combinations
A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates...
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6115778 |
Method and apparatus for handling interrupts through the use of a vector access signal
A control system comprises an interrupt controller, having vector access signal output mechanism for outputting a vector access signal, which is activated when a start address is read out from a...
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6115775 |
Method and apparatus for performing interrupt frequency mitigation in a network node
A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A...
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6115779 |
Interrupt management system having batch mechanism for handling interrupt events
An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request...
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6113651 |
Compile method, a compiler, an exception handler, and a program recording medium
The present invention provides a compile method comprising steps of allocating a variable which is living and may be used after processing by an exception processing program, to a register whose...
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6112273 |
Method and apparatus for handling system management interrupts (SMI) as well as, ordinary interrupts of peripherals such as PCMCIA cards
An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit...
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6112274 |
Method and apparatus for processing more than one interrupts without reinitializing the interrupt handler program
A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage...
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6112260 |
Method and apparatus for redirecting input/output device data in a computer system through use of debug registers
A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer...
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6108389 |
Synchronization of internal coder-decoders of multiple microprocessors
A method and apparatus of bringing sampling instants of a first internal coder-decoder (14) of a first microprocessor (10) into synchronization with sampling instants of a second internal...
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6108755 |
Asynchronous access system to a shared storage
The present invention relates to an asynchronous access system for accessing a shared storage in a multiprocessor system in which a plurality of processor modules and shared storage modules are...
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6108699 |
System and method for modifying membership in a clustered distributed computer system and updating system configuration
Multiple nodes can concurrently gain membership in a cluster of nodes of a distributed computer system by broadcasting reconfiguration messages to all nodes of the distributed computer system. In...
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6105101 |
16 bit bios interrupt calls under 32 bit protected mode application
A method for performing 16 Bit BIOS interrupt calls under a 32 Bit protected mode application. This has been impossible to-date and has forced BIOS development teams to add support into the BIOS...
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6105102 |
Mechanism for minimizing overhead usage of a host system by polling for subsequent interrupts after service of a prior interrupt
An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines,...
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6105081 |
UART character matching used for address matching on a register-by-register basis
An asynchronous serial port is provided in a microcontroller that includes an address matching function that includes character matching functions such that incoming data is compared to match...
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6101571 |
Circuit configuration for generating an interrupt signal for a microprocessor
A circuit configuration for generating an interrupt signal for a microprocessor includes a multiplicity of signal generating circuits that are connected to one another via a logic combination...
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6098143 |
Remote server management device
A computer system includes a bus, remote console logic, a remote server management device, and an interrupt routing switch. The bus has a first interrupt line. The remote console logic has a second...
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6092144 |
Method and system for interrupt-responsive execution of communications protocols
A method and system for interrupt-responsive execution of a communications protocol which obtains data sent by a sending computer a receiving computer via a communications interface. An interrupt...
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6092143 |
Mechanism for synchronizing service of interrupts by a plurality of data processors
An apparatus and method ensure that only one data processor, within a multiprocessor system, performs operations associated with an interrupt register having information corresponding to a...
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6085218 |
Monitoring processor execution cycles to prevent task overrun in multi-task, hard, real-time system
Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor...
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6085308 |
Protocol processor for the execution of a collection of instructions in a reduced number of operations
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor...
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6081861 |
PCI migration support of ISA adapters
A method and implementing system are provided which includes a PCI host bridge connected to a PCI bus. The PCI slots are applied to a switch array which is controlled by circuitry within the PCI...
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6081866 |
Interruptible state machine
An interruptible state machine includes a state machine and an interrupt processor. The interrupt processor minimizes the required total number of states for the state machine when it must return...
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6081867 |
Software configurable technique for prioritizing interrupts in a microprocessor-based system
A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an...
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6078969 |
Information processing device and method for sequence control and data processing
An information processing device includes a general-purpose personal computer 200, and a sequence engine 300 having a rudder interpreter 301 connected to the general-purpose personal computer 200...
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6078970 |
System for determining adapter interrupt status where interrupt is sent to host after operating status stored in register is shadowed to host memory
An I/O adapter connects an I/O adapter to an I/O bus and includes a device interrupt status register and an interrupt status shadow address register. The device interrupt status register stores the...
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6076133 |
Computer interface with hardwire button array
The invention is a computer interface with a hardwired button array on the computer chassis for simulating the apparatus of common consumer electronic devices. Each button of the array of buttons...
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6070218 |
Interrupt capture and hold mechanism
A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an...
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6065122 |
Smart battery power management in a computer system
A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management...
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6061710 |
Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
A method of using multithreading resources for improving handling instructions is operated by an improved multithreaded processor which includes a context select logic unit being arranged and...
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6047351 |
Jitter free instruction execution
A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program...
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6044305 |
Method and apparatus for debugging and tuning a process control network having distributed control functions
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6038607 |
Method and apparatus in a computer system having plural computers which cause the initiation of functions in each other using information contained in packets transferred between the computers
To reduce an overhead of the interrupt on a processor associated with packet send and receive control in a network, a packet send command chaining unit is provided. Based on the control field in...
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6038631 |
Data processing system and method using virtual storage system
In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence...
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